Xilinx LogiCORE 1000BASE-X - Page 28

28 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 2: Core Architecture
R
Figure 2-4 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core using
a RocketIO transceiver without the optional PCS Management Registers
Figure 2-4: Component Pinout Using RocketIO Transceiver
without PCS Management Registers
mgt_rx_reset
signal_detect
rxbufstatus[1:0]
rxchariscomma
rxcharisk
RocketIO Interface
mgt_tx_reset
rxclkcorcnt[2:0]
rxdata[7:0]
rxdisperr
rxnotintable
rxrundisp
txbuferr
userclk
dcm_locked
userclk2
powerdown
txchardispmode
txchardispval
txcharisk
txdata
enablealign
gmii_rxd[7:0]
gmii_txd[7:0]
gmii_tx_en
gmii_tx_er
reset
gmii_rx_dv
gmii_rx_er
GMII
gtx_clk
gmii_isolate
configuration_vector[3:0]
MDIO Replacement
status_vector[4:0]