VC709 BIST Design Description
Block Design IP
– Processor and Subsystems: MicroBlaze, MicroBlaze Debug Module (MDM),
Local Memory Bus, LMB BRAM Controller, Block Memory Generator, Proc Sys
Reset, AXI Interrupt Controller
– AXI Bus: AXI Interconnect, AXI Timer
– Memory: AXI BRAM Controller, MIG 7 Series
– Peripherals: AXI EMC, AXI IIC, AXI GPIO, AXI UART 16550, XADC Wizard
– Other IP: Constant, Concat, gte2_top
• Vivado Design Suite Tcl Command Reference Guide (UG835)
• Designing IP Subsystems Using IP Integrator (UG994)
Note: Presentation applies to the VC709
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