Xilinx VCU1525 User Manual

VCU1525 Acceleration Platform User Guide 30
UG1268 (v1.0) November 13, 2017 www.xilinx.com
Chapter 3: Board Component Descriptions
• Four GTY transceivers (bank 227) are wired to PCIe edge connector CN1 lanes 3:0.
The GTY transceivers in the XCVU9P-L2FSGD2104E are grouped into four channels or quads.
The reference clock for a quad can be sourced from the quad above or the quad below the
GTY quad of interest. The six GTY quads used on the VCU1525 board have the following
connectivity (also see Figure 3-10):
Quad 231:
• MGTREFCLK0 - MGT_SI570_CLOCK0_C_P/N
•MGTREFCLK1 - QSFP0_CLOCK_P/N
• Contains four GTY transceivers allocated to QSFP0 TX/RX lanes 1:4
Quad 230:
• MGTREFCLK0 - MGT_SI570_CLOCK1_C_P/N
•MGTREFCLK1 - QSFP1_CLOCK_P/N
• Contains four GTY transceivers allocated to QSFP1 TX/RX lanes 1:4
Quad 224:
• MGTREFCLK0 - not connected
• MGTREFCLK1 - not connected
• Contains four GTY transceivers allocated to PCIe lanes 15:12
Quad 225:
• MGTREFCLK0 - not connected
• MGTREFCLK1 - not connected
• Contains four GTY transceivers allocated to PCIe lanes 11:8
Quad 226:
• MGTREFCLK0 - PEX_REFCLK_C_P/N unbuffered PCIe edge connector clock
• MGTREFCLK1 - not connected
• Contains four GTY transceivers allocated to PCIe lanes 7:4
Quad 227:
• MGTREFCLK0 - not connected
• MGTREFCLK1 - not connected
• Contains four GTY transceivers allocated to PCIe lanes 3:0
Send Feedback

Xilinx VCU1525 Specifications

General

Brand	Xilinx
Model	VCU1525
Category	Microcontrollers
Language	English