Xilinx VCU1525 User Manual

VCU1525 Acceleration Platform User Guide 19
UG1268 (v1.0) November 13, 2017 www.xilinx.com
Chapter 3: Board Component Descriptions
USB JTAG Interface
[Figure 2-1, callout 7]
The VCU1525 board XCVU9P-L2FSGD2104E FPGA U13 is the only component in the Joint
Test Action Group (JTAG) chain. JTAG configuration is available through the USB-to-JTAG
FTDI FT4232HQ U27 bridge device connected to Micro-AB USB connector J13. The FTDI
JTAG signals are level-shifted through TXBN0304 device U35. The PCIe 16-lane edge
connector CN1 JTAG port is connected in parallel through level-shifter U34. GPIO port 3 of
the U19 MSP432 BMC is also connected through level-shifter U33. Each level-shifter enable
pin is controlled by the BMC to allow only one JTAG connection at a time.
JTAG configuration is allowed at any time regardless of the FPGA mode pin settings.
The JTAG chain block diagram is shown in Figure 3-3.
For more details about the FT4232HQ device, see the FTDI website [Ref 6].
X-Ref Target - Figure 3-3
Figure 3-3: VCU1525 JTAG Chain Block Diagram
FT4232HQ
USB AB
J13
U27
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS5
TXBN0304
U35
B1
B3
B2
B4
A1
A3
A2
A4
OE_B
3.3V L/S 1.8V
FT TCK
FT TDO
FT TDI
FT TMS
FT OE
XCVU9PFSGD2104
U13R
TCK
TDI
TDO
TMS
BANK 0
TCK
TDI
TDO
TMS
MSP432
U19
P3_0
P3_1
P3_2
P3_3
P3_4
TXBN0304
U33
B1
B3
B2
B4
A1
A3
A2
A4
OE_B
3.3V L/S 1.8V
MSP TCK
MSP TDI
MSP TDO
MSP TMS
MSP EN
PCIe EDGE
CN1
A5
A6
A7
A8
TXBN0304
U34
B1
B3
B2
B4
A1
A3
A2
A4
OE_B
3.3V L/S 1.8V
PEX TCK
PEX TDI
PEX TDO
PEX TMS
P10_4
SYSTEM
CONTROLLER
PEX OE
TCK
TDI
TDO
TMS
GPIO
PORT
TCK
TDI
TDO
TMS
X19965-103017
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Xilinx VCU1525 Specifications

General

Brand	Xilinx
Model	VCU1525
Category	Microcontrollers
Language	English