Xilinx VCU1525

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VCU1525 Acceleration Platform User Guide 67

UG1268 (v1.0) November 13, 2017 www.xilinx.com

Appendix A: Master Constraints File Listing

set_property PACKAGE_PIN N13 [get_ports DDR4_C3_DQ66];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C3_DQ66];

set_property PACKAGE_PIN N14 [get_ports DDR4_C3_DQ67];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C3_DQ67];

set_property PACKAGE_PIN T15 [get_ports DDR4_C3_DQ68];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C3_DQ68];

set_property PACKAGE_PIN R15 [get_ports DDR4_C3_DQ69];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C3_DQ69];

set_property PACKAGE_PIN P13 [get_ports DDR4_C3_DQ70];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C3_DQ70];

set_property PACKAGE_PIN P14 [get_ports DDR4_C3_DQ71];

set_property IOSTANDARD POD12_DCI [get_ports DDR4_C3_DQ71];

set_property PACKAGE_PIN R22 [get_ports DDR4_C3_DQS_C0];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_C0];

set_property PACKAGE_PIN T22 [get_ports DDR4_C3_DQS_T0];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_T0];

set_property PACKAGE_PIN H21 [get_ports DDR4_C3_DQS_C1];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_C1];

set_property PACKAGE_PIN J21 [get_ports DDR4_C3_DQS_T1];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_T1];

set_property PACKAGE_PIN K20 [get_ports DDR4_C3_DQS_C2];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_C2];

set_property PACKAGE_PIN L20 [get_ports DDR4_C3_DQS_T2];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_T2];

set_property PACKAGE_PIN P18 [get_ports DDR4_C3_DQS_C3];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_C3];

set_property PACKAGE_PIN P19 [get_ports DDR4_C3_DQS_T3];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_T3];

set_property PACKAGE_PIN A24 [get_ports DDR4_C3_DQS_C4];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_C4];

set_property PACKAGE_PIN A25 [get_ports DDR4_C3_DQS_T4];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_T4];

set_property PACKAGE_PIN B17 [get_ports DDR4_C3_DQS_C5];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_C5];

set_property PACKAGE_PIN C17 [get_ports DDR4_C3_DQS_T5];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_T5];

set_property PACKAGE_PIN F17 [get_ports DDR4_C3_DQS_C6];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_C6];

set_property PACKAGE_PIN F18 [get_ports DDR4_C3_DQS_T6];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_T6];

set_property PACKAGE_PIN E23 [get_ports DDR4_C3_DQS_C7];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_C7];

set_property PACKAGE_PIN F23 [get_ports DDR4_C3_DQS_T7];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_T7];

set_property PACKAGE_PIN P15 [get_ports DDR4_C3_DQS_C8];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_C8];

set_property PACKAGE_PIN R16 [get_ports DDR4_C3_DQS_T8];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_T8];

set_property PACKAGE_PIN N21 [get_ports DDR4_C3_DQS_C9];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_C9];

set_property PACKAGE_PIN N22 [get_ports DDR4_C3_DQS_T9];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_T9];

set_property PACKAGE_PIN L22 [get_ports DDR4_C3_DQS_C10];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_C10];

set_property PACKAGE_PIN M22 [get_ports DDR4_C3_DQS_T10];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_T10];

set_property PACKAGE_PIN K17 [get_ports DDR4_C3_DQS_C11];

set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_C11];

set_property PACKAGE_PIN K18 [get_ports DDR4_C3_DQS_T11];

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