Xilinx VCU1525

VCU1525 Acceleration Platform User Guide 70
UG1268 (v1.0) November 13, 2017 www.xilinx.com
Appendix A: Master Constraints File Listing
# PCIE PERST
set_property PACKAGE_PIN BD21 [get_ports PCIE_PERST_LS];
set_property IOSTANDARD LVCMOS12 [get_ports PCIE_PERST_LS];
# FPGA-TO-MSP432 (U19) UART CHANNEL
set_property PACKAGE_PIN BA19 [get_ports FPGA_RXD_MSP];
set_property IOSTANDARD LVCMOS12 [get_ports FPGA_RXD_MSP];
set_property PACKAGE_PIN BB19 [get_ports FPGA_TXD_MSP];
set_property IOSTANDARD LVCMOS12 [get_ports FPGA_TXD_MSP];
# FPGA-TO-MSP432 (U19) 4-WIRE GPIO CHANNEL
set_property PACKAGE_PIN AR20 [get_ports GPIO_MSP0];
set_property IOSTANDARD LVCMOS12 [get_ports GPIO_MSP0];
set_property PACKAGE_PIN AM20 [get_ports GPIO_MSP1];
set_property IOSTANDARD LVCMOS12 [get_ports GPIO_MSP1];
set_property PACKAGE_PIN AM21 [get_ports GPIO_MSP2];
set_property IOSTANDARD LVCMOS12 [get_ports GPIO_MSP2];
set_property PACKAGE_PIN AN21 [get_ports GPIO_MSP3];
set_property IOSTANDARD LVCMOS12 [get_ports GPIO_MSP3];
# SYSMON I2C
set_property PACKAGE_PIN AR25 [get_ports SYSMON_SCL];
set_property IOSTANDARD LVCMOS12 [get_ports SYSMON_SCL];
set_property PACKAGE_PIN AR26 [get_ports SYSMON_SDA];
set_property IOSTANDARD LVCMOS12 [get_ports SYSMON_SDA];
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