Xilinx Virtex-7 FPGA VC7203 User Manual

VC7203 IBERT Getting Started Guide www.xilinx.com 35
UG847 (v3.0) July 10, 2013
Creating the GTX IBERT Core
12. The SuperClock-2 source code now needs to be added to the example ibert wrapper.
Double-click example_ibert_7series_gtx_0 in the Design Sources to open the verilog
code. Add the top level ports from top_scm2.v to the module declaration and
instantiate the top_scm2 module in the example ibert wrapper (Figure 1-29). Click
File > Save File.
X-Ref Target - Figure 1-28
Figure 1-28: Sources after Running add_scm2.tcl
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Xilinx Virtex-7 FPGA VC7203 Specifications

General

FPGA Family	Virtex-7
Device	XC7VX485T
Transceivers	16
Maximum Transceiver Speed	12.5 Gbps
Transceiver Type	GTX
DSP Slices	2, 800
Block RAM	37, 080 KB
Clock Management Tiles	12
PCIe Gen2/Gen3 Support	Yes
Package	FFG1761