Xilinx Zynq UltraScale+ User Manual

Zynq UltraScale+ VCU TRD User Guide 47
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 3: APU Software Platform
The following steps are performed in DMA buffer sharing.
In the capture-encode side:
1. The V4L2 capture device (the client driver) allocates buffer.
2. The v4l2src plug-in exports/imports the DMA buffer to the gst-omx plug-in.
3. The gst-omx plug-in passes the file descriptor to the encoder driver.
4. The encoder driver uses the DMA_BUF framework and reads the kernel buffer for
encoding.
In the playback side:
1. The decoder driver allocates DMA buffer.
2. The gst-omx plug-in exports the file descriptor (FD) to the kmssink plug-in.
3. The kmssink plug-in passes the file descriptor to the DisplayPort controller driver.
4. The DisplayPort driver uses the kernel DMA_BUF framework to know the decoder buffer
location.
5. The DisplayPort DMA reads the decoded buffer without copying the buffer in kernel
memory.
X-Ref Target - Figure 3-20
Figure 3-20: Buffer Sharing
Video capture
V4L2 VCU DRM/KMS
DMABUF
Video
encode/decode
Display
X19445-112718
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Xilinx Zynq UltraScale+ Specifications

General

Manufacturer	Xilinx
Model	Zynq UltraScale+
Category	SoC
Processor Cores	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
FPGA Fabric	UltraScale+ FPGA
Memory Interfaces	DDR4, DDR3, LPDDR3, LPDDR4
Connectivity	Gigabit Ethernet, USB 3.0, SATA, PCIe
Video Codecs	H.264
Power Consumption	Varies depending on specific device configuration and usage
Operating Temperature	Commercial: 0°C to +85°C, Industrial: -40°C to +100°C