Xilinx Zynq UltraScale+ User Manual

Zynq UltraScale+ VCU TRD User Guide 46
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 3: APU Software Platform
Video Buffer Management
In the case of a raw/processed pipeline, the video capture device (v4l2src), video processing
accelerator (VCU element), and kmssink plugin use DMABUF framework for sharing buffers
between peer elements (see Figure 3-20).
X-Ref Target - Figure 3-19
Figure 3-19: Multi-Stream—7 HDMI and 1 MIPI Input Sources @ 1080p30
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Xilinx Zynq UltraScale+ Specifications

General

Manufacturer	Xilinx
Model	Zynq UltraScale+
Category	SoC
Processor Cores	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
FPGA Fabric	UltraScale+ FPGA
Memory Interfaces	DDR4, DDR3, LPDDR3, LPDDR4
Connectivity	Gigabit Ethernet, USB 3.0, SATA, PCIe
Video Codecs	H.264
Power Consumption	Varies depending on specific device configuration and usage
Operating Temperature	Commercial: 0°C to +85°C, Industrial: -40°C to +100°C