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General| Manufacturer | Xilinx |
|---|---|
| Model | Zynq UltraScale+ |
| Category | SoC |
| Processor Cores | Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5 |
| FPGA Fabric | UltraScale+ FPGA |
| Memory Interfaces | DDR4, DDR3, LPDDR3, LPDDR4 |
| Connectivity | Gigabit Ethernet, USB 3.0, SATA, PCIe |
| Video Codecs | H.264 |
| Power Consumption | Varies depending on specific device configuration and usage |
| Operating Temperature | Commercial: 0°C to +85°C, Industrial: -40°C to +100°C |
Describes the features and functions of the Zynq UltraScale+ MPSoC VCU TRD.
Summarizes the nine design modules (DMs) comprising the VCU TRD.
Shows the APU Linux software platform layers: Application, Middleware, OS, and HW.
VCU core supports H.264/H.265 encoding/decoding via CtrlSW, OMX IL, and GStreamer.
Xilinx PCI Express DMA (XDMA) IP for high-performance scatter gather DMA.
Describes the non-secure boot flow and SD boot mode sequence.
Location of system addresses for reference.
Describes the TRD hardware architecture and ZCU106/daughter card components.
Describes the clocking mechanism using MMCM, VCU PLL, and reference clocks.
Address map for various IP blocks in PL for the VCU TRD.
Describes the file format of the input configuration file (input.cfg).
Access Xilinx documents, videos, and support resources.
Lists websites and documents providing supplemental material for the design.
Legal disclaimer regarding the materials and Xilinx products.
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