Xilinx Zynq UltraScale+ User Manual

Zynq UltraScale+ VCU TRD User Guide 57
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 5: Hardware Platform
Note: The audio design uses pl_clk1 as the Video Pixel clock (instead of MMCM output) for both TX
and RX pipelines. The Ethernet 10G design uses the SPF_SI5328_OUT clock from the board as the
DRU clock, because USER_MGT_SI570_CLOCK is used by the Ethernet Subsystem as the GT reference
clock.
Reset
A synchronous reset mechanism is used in the TRD. PL_RESET0 is used as a master reset
signal. Interconnect and peripheral reset signals are generated using proc_sys_rst IP in the
PL. The VCU Reset in PCIe design is gated with the link_up signal of the PCIe Endpoint block.
X-Ref Target - Figure 5-2
Figure 5-2: Clocking Mechanism for the TRD
Processing
System
pl_clk1
pl_clk0
MMCM
Si570_user
Ethernet Rx
Audio
Formatter Rx
TPG
MIPI Rx
SDI Rx
HDMI Rx
Ethernet Tx
Audio
Formatter Tx
SDI Tx
HDMI Tx
Input/Capture
Output/Display
Hardware
Accelerator
VCU
Processing
MIPI dphy Clock
VCU Reference Clock
Ethernet GT reference clock
DRU/SDI GT reference clock
Video Pixel Clock
Audio Clock
I2S Tx
I2S Rx
VCU DDR4
Controller
MIG Clock
User Clk
X19306-042419
Send Feedback

Xilinx Zynq UltraScale+ Specifications

General

Manufacturer	Xilinx
Model	Zynq UltraScale+
Category	SoC
Processor Cores	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
FPGA Fabric	UltraScale+ FPGA
Memory Interfaces	DDR4, DDR3, LPDDR3, LPDDR4
Connectivity	Gigabit Ethernet, USB 3.0, SATA, PCIe
Video Codecs	H.264
Power Consumption	Varies depending on specific device configuration and usage
Operating Temperature	Commercial: 0°C to +85°C, Industrial: -40°C to +100°C