Xilinx Zynq UltraScale+ User Manual

Zynq UltraScale+ VCU TRD User Guide 53
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 4: System Considerations
The active area is the part of the video buffer that is visible on the screen. The active area is
defined by the height and width parameters, also called the video dimensions. Those are
typically expressed in number of pixels because the bits per pixel depend on the pixel
format as explained above.
The stride or pitch is the number of bytes from the first pixel of a line to the first pixel of the
next line of video. In the simplest case, the stride equals the width multiplied by the bits per
pixel, converted to bytes. For example, AR24 requires 32 BPP which is four bytes per pixel.
A video buffer with an active area of 1920 x 1080 pixels therefore has a stride of
4 x 1920 = 7,680 bytes. Some DMA engines require the stride to be a power of two to
optimize memory accesses. In this design, the stride always equals the width in bytes.
X-Ref Target - Figure 4-2
Figure 4-2: Video Buffer Area
x-offset
y-offset
height
width
stride
fb
Active Area
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Xilinx Zynq UltraScale+ Specifications

General

Manufacturer	Xilinx
Model	Zynq UltraScale+
Category	SoC
Processor Cores	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
FPGA Fabric	UltraScale+ FPGA
Memory Interfaces	DDR4, DDR3, LPDDR3, LPDDR4
Connectivity	Gigabit Ethernet, USB 3.0, SATA, PCIe
Video Codecs	H.264
Power Consumption	Varies depending on specific device configuration and usage
Operating Temperature	Commercial: 0°C to +85°C, Industrial: -40°C to +100°C