Yamaha DSP-E800 - Page 30

DSP-E800
DSP-E800
27
IC6 : AK4526A-VQ (CODEC. ADC/DAC)
20-bit 6-channel A/D, D/A Converter
VR
VR
VR
VR
VR
VR
LPF DAC
LPF DAC
LPF DAC
LPF DAC
LPF DAC
LPF DAC
SDOS
OCKS
M/S
BICK
LRCK
SDTI1
SDTI2
SDTI3
SDTO
DAUX
DFS
DEM1 DEM0
MCKO
DVDD
DVSS
/PD
XTS
ICKS1 ICKS0
CAD1 CAD0
CDTO CDTI CCLK /CS P/S MCKI XTI AVSS AVDD VREFH VCOM
VREFL
RIN+
RIN–
LIN+
LIN–
ROUT1
LOUT1
ROUT2
LOUT2
ROUT3
LOUT3
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
34 35 36 37 38 39 40 41 42 43 44
23
24
25
26
27
28
29
30
31
32
33
13
12
11
1
6
9
7
8
25
26
23
24
DEM0
10
DAUX
SDIN3
SDIN2
SDIN1
SDOUT
BICK
LRCK
MCLK
DEM1
2
14
OCKS MCKO
DFS
SDTO
SDOS
SDTI1
LOUT2
LOUT2
28
ROUT1
27
LOUT1
31
RIN–
ROUT2
ROUT3
SDTI2
SDTI3
TOP VIEW
39
5
4
MCKI
LRCK
BICK
32
RIN+
29
LIN–
30
LIN+
1/2
Audio
I/F
ADC HPF
DEM
Clock Gen.
ADC HPF
Pin Pin
I/O Function
No. Name
1 SDOS I Fixed L
2 OCKS I Fixed L
3 M/S I Fixed L
4 BICK I
Audio serial data clock,
64fs bit clock input from microcomputer
5 LRCK I
L/R channel clock,
1fs word clock input from microcomputer
6 SDTI1 I
DAC Audio serial data input 1-3,
PCM input from AC3D2av
7 SDTI2 I
8 SDTI3 I
9 SDTO O
Audio serial data output,audio
data for AC3D2av
10 DAUX I Fixed L
11 DFS I Double speed sampling mode selection
data input from DIR5
12 DEM1 I
De-emphasis frequency select input 1 (Fixed L)
De-emphasis frequency select input 0 (Fixed L)
13 DEM0 I
14 MCKO O Unconnected
15 DVDD Power supply (digital)
16 DVSS Ground (digital)
17 /PD I Power-down and reset, initial clear input
from AC3D2av
18 XTS I Connected to ground (analog)
19 ICKS1 I Connected to ground (analog)
20 ICKS0 I Connected to ground (analog)
21 CAD1 I Connected to ground (analog)
22 CAD0 I Connected to ground (analog)
44 CDTO O Unconnected
Pin Pin
I/O Function
No. Name
23 LOUT3 O
O
Lch analog output 3, for CENTER
Rch analog output 3, for LFE
24 ROUT3
25 LOUT2 O
O
Lch analog output 2, for REAR
26 ROUT2 Rch analog output 2, for REAR
27 LOUT1 O Lch analog output 1, for FRONT
28 ROUT1 O Rch analog output 1, for FRONT
29 LIN– I Lch negative analog input, from MAIN
30 LIN+ I Lch positive analog input, from MAIN
31 RIN– I Rch negative analog input, from MAIN
32 RIN+ I Rch positive analog input, from MAIN
33 VREFL I Reference voltage (Low) input (analog)
34 VCOM O Common voltage output
35 VREFH I
I
Reference voltage (High) input (analog)
36 AVDD Power supply (analog)
37 AVSS Ground (analog)
38 XTI Unconnected
39 MCKI
External master clock input, 256fs bit
clock input from DIR5
40 P/S I Fixed L
41 /CS I
Chip select in serial mode, chip enable
from microcomputer
42 CCLK I
Control data clock in serial mode,
serial clock from microcomputer
43 CDTI I
Control data input in serial mode,
serial data from microcomputer