Pin
No.
Function Name
TYPE
(1)
PULL
(2)
Detail of Function
M14 EMA_WE_DQM[0] /UHPI_HINT/AXR0[15]/GP2[9] O IPU EMIFA write enable/data mask for EMA_D[7:0]
R7 EMA_OE /UHPI_HDS1/AXR0[13]/GP2[7] O IPU EMIFA output enable
N6 EMA_WAIT[0]/ UHPI_HRDY/GP2[10] I IPU EMIFA wait input/interrupt
External Memory Interface B (only SDRAM )
G14 EMB_D[31] I/O IPD EMIFB SDRAM data bus
F15 EMB_D[30] I/O IPD
F14 EMB_D[29] I/O IPD
E15 EMB_D[28] I/O IPD
E14 EMB_D[27] I/O IPD
A14 EMB_D[26] I/O IPD
B14 EMB_D[25] I/O IPD
A13 EMB_D[24] I/O IPD
L15 EMB_D[23] I/O IPD
L14 EMB_D[22] I/O IPD
K16 EMB_D[21] I/O IPD
K13 EMB_D[20] I/O IPD
J14 EMB_D[19] I/O IPD
H15 EMB_D[18] I/O IPD
H14 EMB_D[17] I/O IPD
G15 EMB_D[16] I/O IPD
F13 EMB_D[15]/GP6[15] I/O IPD
E16 EMB_D[14]/GP6[14] I/O IPD
E13 EMB_D[13]/GP6[13] I/O IPD
D16 EMB_D[12]/GP6[12] I/O IPD
D15 EMB_D[11]/GP6[11] I/O IPD
D14 EMB_D[10]/GP6[10] I/O IPD
D13 EMB_D[9]/GP6[9] I/O IPD
C16 EMB_D[8]/GP6[8] I/O IPD
J16 EMB_D[7]/GP6[7] I/O IPD
J15 EMB_D[6]/GP6[6] I/O IPD
J13 EMB_D[5]/GP6[5] I/O IPD
H16 EMB_D[4]/GP6[4] I/O IPD
H13 EMB_D[3]/GP6[3] I/O IPD
G16 EMB_D[2]/GP6[2] I/O IPD
G13 EMB_D[1]/GP6[1] I/O IPD
F16 EMB_D[0]/GP6[0] I/O IPD
B15 EMB_A[12]/GP3[13] O IPD EMIFB SDRAM row/column address bus
B12 EMB_A[11]/GP7[13] O IPD
A9 EMB_A[10]/GP7[12] O IPD
C12 EMB_A[9]/GP7[11] O IPD
D12 EMB_A[8]/GP7[10] O IPD
A11 EMB_A[7]/GP7[9] O IPD
B11 EMB_A[6]/GP7[8] O IPD
C11 EMB_A[5]/GP7[7] O IPD
D11 EMB_A[4]/GP7[6] O IPD EMIFB SDRAM row/column address
A10 EMB_A[3]/GP7[5] O IPD
B10 EMB_A[2]/GP7[4] O IPD
C10 EMB_A[1]/GP7[3] O IPD
D10 EMB_A[0]/GP7[2] O IPD
B9 EMB_BA[1]/GP7[0] O IPU EMIFB SDRAM bank address
C9 EMB_BA[0]/GP7[1] O IPU
C14 EMB_CLK O IPU EMIF SDRAM clock
C13 EMB_SDCKE I/O IPU EMIFB SDRAM clock enable
K15 EMB_WE O IPU EMIFB write enable
A8 EMB_RAS O IPU EMIFB SDRAM row address strobe
L13 EMB_CAS O IPU EMIFB column address strobe
D9 EMB_CS[0] O IPU EMIFB SDRAM chip select 0
A12 EMB_WE_DQM[3] O IPU EMIFB write enable/data mask for EMB_D
B13 EMB_WE_DQM[2] O IPU
C15 EMB_WE_DQM[1] /GP5[14] O IPU
K14 EMB_WE_DQM[0] /GP5[15] O IPU
Serial Peripheral Interface Modules (SPI0, SPI1)
N4 SPI0_SCS[0] /UART0_RTS/EQEP0B/GP5[4]/ I/O IPU SPI0 chip select
BOOT[4]
R5
SPI0_ENA /UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
I/O IPU SPI0 enable
T5 SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] I/O IPD SPI0 clock
P6 SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] I/O IPD SPI0 data/slave-in-master-out
93
YSP-CU4300/YSP-CU3300/NS-WSW160
YSP-CU4300/YSP-CU3300/
NS-WSW160