Yamaha YSP-4300 - Page 94

Pin
No.
Function Name
TYPE
(1)
PULL
(2)
Detail of Function
R6 SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] I/O IPD SPI0 data/slave-out-master-in
P4 SPI1_SCS[0] /UART2_TXD/GP5[13] I/O IPU SPI1 chip select
R4 SPI1_ENA /UART2_RXD/GP5[12] I/O IPU SPI1 enable
T6 SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] I/O IPD SPI1 clock
N5 SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] I/O IPU SPI1 data/slave-in-master-out
P5 SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] I/O IPU SPI1 data/slave-out-master-in
Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
C5 ACLKX0/ECAP0/APWM0/GP2[12] I/O IPD Enhanced capture 0/input or auxiliary PWM 0 output
B4 ACLKR0/ECAP1/APWM1/GP2[15] I/O IPD Enhanced capture 1/input or auxiliary PWM 1 output
L2 ACLKR1/ECAP2/APWM2/GP4[12] I/O IPD Enhanced capture 2/input or auxiliary PWM 2 output
Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
K3 ACLKX1/EPWM0A/GP3[15] I/O IPD eHRPWM0 A output
K2 AHCLKX1/EPWM0B/GP3[14] I/O IPD eHRPWM0 B output
D4 AMUTE1/EPWMTZ/GP4[14] I/O IPD eHRPWM0 trip zone input
K4 AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10] I/O IPD
Sync input to eHRPWM0 module or sync output to external PWM
M2 AXR1[8]/EPWM1A/GP4[8] I/O IPD eHRPWM1 A (with high-resolution)
M3 AXR1[7]/EPWM1B/GP4[7] I/O IPD eHRPWM1 B
D4 AMUTE1/EPWMTZ/GP4[14] I/O IPD eHRPWM1 trip zone input
M4 AXR1[6]/EPWM2A/GP4[6] I/O IPD eHRPWM2 A (with high-resolution)
N1 AXR1[5]/EPWM2B/GP4[5] I/O IPD eHRPWM2 B
D4 AMUTE1/EPWMTZ/GP4[14] I/O IPD eHRPWM2 trip zone input
Enhanced Quadrature Encoder Pulse Module (eQEP)
R5 SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/ I IPU eQEP0A quadrature input
BOOT[3]
N4 SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/ I IPU eQEP0B quadrature input
BOOT[4]
R6 SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] I IPD eQEP0 index
P6 SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] I IPD eQEP0 strobe
P1 AXR1[3]/EQEP1A/GP4[3] I IPD eQEP1A quadrature input
N2 AXR1[4]/EQEP1B/GP4[4] I IPD eQEP1B quadrature input
T5 SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] I IPD eQEP1 index
T6 SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] I IPD eQEP1 strobe
Boot
P7 EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15] I IPU BOOT[15]
M13
EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14] I IPU BOOT[14]
M15 EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/ I IPU BOOT[13]
BOOT[13]
T13 EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/ I IPU BOOT[12]
BOOT[12]
A4 AHCLKR0/GP2[14]/BOOT[11] I IPD BOOT[11]
D5 AFSX0/GP2[13]/BOOT[10] I IPD BOOT[10]
P3 UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/ I IPU BOOT[9]
BOOT[9]
R3 UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/ I IPU BOOT[8]
BOOT[8]
T6 SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] I IPD BOOT[7]
N5 SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] I IPU BOOT[6]
P5 SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] I IPU BOOT[5]
N4 SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/ I IPU BOOT[4]
BOOT[4]
R5 SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/ I IPU BOOT[3]
BOOT[3]
T5 SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] I IPD BOOT[2]
P6 SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] I IPD BOOT[1]
R6 SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] I IPD BOOT[0]
Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
R3 UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/ I IPU UART0 receive data
BOOT[8]
P3 UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/ O IPU UART0 transmit data
BOOT[9]
N4 SPI0_SCS[0]/ UART0_RTS /EQEP0B/GP5[4]/ O IPU UART0 ready-to-send output
BOOT[4]
R5 SPI0_ENA/ UART0_CTS /EQEP0A/GP5[3]/ I IPU UART0 clear-to-send input
BOOT[3]
C6 UART1_RXD/AXR0[9]/GP3[9] (4) I IPD UART1 receive data
D6 UART1_TXD/AXR0[10]/GP3[10] (4) O IPD UART1 transmit data
R4 SPI1_ENA/UART2_RXD/GP5[12] I IPU UART2 receive data
P4 SPI1_SCS[0]/UART2_TXD/GP5[13] O IPU UART2 transmit data
94
YSP-CU4300/YSP-CU3300/NS-WSW160
YSP-CU4300/YSP-CU3300/
NS-WSW160
DRAFT