Figure 3. Pipeline Example
Clock
Address
Note: F & D = Fetch & Decode
Data In
Command
Execution
State
INC A Fetch Decode
Prefetch
Execute
F & D F & D Decode
Next command
1 clock delay for execution
Prefetch
Execute
LD (1234h), A
LD (5678h), A
INC A
Data Out
INST_READ
MEM_READ
MEM_WRITE
PC
INC A LD (nn), A nL nH LD (nn), A Write nL nH INC A Write
PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 PC+7 5678h1234h
78h(1234h)32h12h (5678h)3Ch56h34h32h3Ch
F & D F & D Decode
Prefetch
Execute
ValidInvalidValidInvalid
Next command
1 clock delay for execution
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