ZiLOG eZ80 User Manual

eZ80
®
CPU
User Manual
UM007714-0908 CPU Instruction Set
149
IM n
Set Interrupt Mode
Operation
Select the appropriate interrupt mode from Interrupt Mode 0, Interrupt Mode 1, and Inter-
rupt Mode 2.
Description
The n operand is any of the following interrupt modes:
• Interrupt Mode 0—in this mode, the interrupting device inserts an instruction on the
data bus during an interrupt acknowledge cycle.
• Interrupt Mode 1—in this mode, the CPU responds to an interrupt by executing a
restart to location
000038h.
• Interrupt Mode 2—in this mode, the interrupting device places the low-order address
of the interrupt vector on the data bus during an interrupt acknowledge cycle. The I
register provides the high-order byte of the interrupt vector table address. The 16-bit
value at the address {I, DATA[7:0]} is the starting address of the interrupt service rou-
tine.
Condition Bits Affected
None.
Attributes
Attributes
Not all eZ80
®
products support the three interrupt modes. Refer to the individual product
specification for information on supported interrupt modes.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
IM 0X2ED, 46
IM 1X2ED, 56
IM 2X2ED, 5E

ZiLOG eZ80 Specifications

General

Brand	ZiLOG
Model	eZ80
Category	Computer Hardware
Language	English