eZ80
®
CPU
User Manual
UM007714-0908 CPU Instruction Set
180
JP cc, Mmn
Conditional Jump
Operation
if
cc
{
PC ← Mmn
}
Description
If the condition is true (a logical 1), the Program Counter, PC, is loaded with the instruc-
tion operand. When assembled, the first byte after the opcode is the low-order byte of the
operand. Table 58 provides more detailed information on this instruction, particularly
when switching between ADL and Z80 modes. The information in Table 58 is only valid
if the condition is true.
Condition Bits Affected
None.
Table 58. JP cc, Mmn Instruction Detail
ADL Suffix Operation (if condition cc is true)
0 None or
.SIS
The starting Program Counter is {MBASE, PC[15:0]}. Write the 2-byte
immediate value {mm, nn}, to PC[15:0]. The ADL mode bit remains
cleared to 0. The ending Program Counter is {MBASE,
PC[15:0]} = {MBASE, mm, nn}.
1 None or
.LIL
The starting Program Counter is PC[23:0]. Write the 3-byte immediate
value {MM, mm, nn}, to PC[23:0]. The ADL mode bit remains set to 1.
The ending Program Counter is PC[23:0] = {MM, mm, nn}.
0 .LIL The starting Program Counter is {MBASE, PC[15:0]}. Write the 3-byte
immediate value {MM, mm, nn}, to PC[23:0]. Set the ADL mode bit to 1.
The ending Program Counter is PC[23:0] = {MM, mm, nn}.
1 .SIS The starting Program Counter is PC[23:0]. Write the 2-byte immediate
value {mm, nn}, to PC[15:0]. Reset the ADL mode bit to 0. The ending
Program Counter is {MBASE, PC[15:0]} = {MBASE, mm, nn}.
X .SIL An illegal suffix for this instruction.
X .LIS An illegal suffix for this instruction.
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