eZ80
®
CPU
User Manual
UM007714-0908 CPU Instruction Set
185
JP Mmn
Jump
Operation
PC ← Mmn
Description
The Program Counter is loaded with the instruction operand. When assembled, the first
byte after the opcode is the low-order byte of the operand. Table 61 provides more detailed
information on this instruction, particularly when switching between ADL and Z80
modes.
Condition Bits Affected
None.
Attributes
Table 61. JP Mmn Instruction Detail
ADL Suffix Operation
0 None
or .SIS
The starting Program Counter is {MBASE, PC[15:0]}. Write the 2-byte
immediate value {mm, nn}, to PC[15:0]. The ADL mode bit remains
cleared to 0. The ending Program Counter is {MBASE,
PC[15:0]} = {MBASE, mm, nn}.
1 None
or .LIL
The starting Program Counter is PC[23:0]. Write the 3-byte immediate
value {MM, mm, nn}, to PC[23:0]. The ADL mode bit remains set to 1.
The ending Program Counter is PC[23:0] = {MM, mm, nn}.
0 .LIL The starting Program Counter is {MBASE, PC[15:0]}. Write the 3-byte
immediate value {MM, mm, nn}, to PC[23:0]. Set the ADL mode bit to 1.
The ending Program Counter is PC[23:0] = {MM, mm, nn}.
1 .SIS The starting Program Counter is PC[23:0]. Write the 2-byte immediate
value {mm, nn}, to PC[15:0]. Reset the ADL mode bit to 0. The ending
Program Counter is {MBASE, PC[15:0]} = {MBASE, mm, nn}.
X .SIL An illegal suffix for this instruction.
X .LIS An illegal suffix for this instruction.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
JP mn 04C3, nn, mm
JP Mmn 15C3, nn, mm, MM
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