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ZiLOG eZ80 User Manual
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eZ80
®
CPU
User Manual
UM007714-0908
CPU Instruction Set
201
LD I, A
Load Interrupt Vector
Operation
I[7:0]
←
A
Description
The CPU writes the c
ontents of the accumulator
, A, to the lower byte of the Interrupt
V
ec-
tor register
, I[7:0].
Condition Bits Affected
None.
Attributes
Mnemonic
Operand
ADL Mode
Cycle
Opcode (hex)
LD
I,A
X
2
ED, 47
209
211
Table of Contents
Default Chapter
4
Table of Contents
4
Manual Objectives
6
About this Manual
6
Intended Audience
6
Manual Organization
6
Manual Conventions
7
Safeguards
9
Introduction
10
Architectural Overview
11
Processor Description
11
Pipeline Description
12
Memory Modes
15
Z80 MEMORY Mode
15
ADL MEMORY Mode
16
Registers and Bit Flags
18
Ez80 ® CPU Working Registers
18
Ez80 ® CPU Control Register Definitions
18
Ez80 ® CPU Control Bits
19
Ez80 CPU Registers in Z80 Mode
20
Ez80 CPU Registers in ADL Mode
21
Ez80 CPU Status Indicators (Flag Register)
23
Memory Mode Switching
27
ADL Mode and Z80 Mode
27
Memory Mode Compiler Directives
27
Opcode Suffixes for Memory Mode Control
27
Single-Instruction Memory Mode Changes
29
Suffix Completion by the Assembler
33
Assembly of the Opcode Suffixes
33
Persistent Memory Mode Changes in ADL and Z80 Modes
34
Mixed-Memory Mode Applications
43
MIXED MEMORY Mode Guidelines
43
Interrupts
45
Interrupt Enable Flags (IEF1 and IEF2)
45
Interrupts in Mixed Memory Mode Applications
45
Ez80 ® CPU Response to a Nonmaskable Interrupt
46
Ez80 CPU Response to a Maskable Interrupt
47
Vectored Interrupts for On-Chip Peripherals
52
Illegal Instruction Traps
55
I/O Space
56
Addressing Modes
57
CPU Instruction Set
61
Ez80 ® CPU Assembly Language Programming Introduction
61
Ez80 ® CPU Instruction Notations
62
Ez80 ® CPU Instruction Classes
63
Instruction Summary
68
Ez80 ® CPU Instruction Set Description
86
Opcode Maps
384
Glossary
391
Index
403
Customer Support
411
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ZiLOG eZ80 Specifications
General
Brand
ZiLOG
Model
eZ80
Category
Computer Hardware
Language
English
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