eZ80
®
CPU
User Manual
UM007714-0908 CPU Instruction Set
239
LDDR
Load and Decrement with Repeat
Operation
repeat {
(DE) ← (HL)
BC ← BC – 1
DE ← DE – 1
HL ← HL – 1
} while (BC ≠ 0)
Description
The CPU writes the contents of the memory location with address contained in the multi-
byte register HL to the memory location with address contained in the multibyte register
DE. The BC, DE, and HL registers decrement. This operation is repeated until BC decre-
ments to 0.
In Z80 mode, the BC register is 16 bits, which allows the LDDR instruction to repeat a
maximum of 65536 (64 K) times. In ADL mode, the BC register is 24 bits, which allows
the LDDR instruction to repeat a maximum of 16,777,216 (16 M) times.
Condition Bits Affected
Attributes
S Not affected.
Z Not affected.
H Reset.
P/V Reset if BC− 1 = 0; set otherwise.
N Reset.
C Not affected.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
LDDR —X 2 + 3 *
BC
ED, B8
LDDR.S —1 3 + 3 *
BC
52, ED, B8
LDDR.L —0 3 + 3 *
BC
49, ED, B8
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