eZ80
®
CPU
User Manual
UM007714-0908 CPU Instruction Set
259
OTDMR
Output to I/O and Decrement
Operation
repeat {
({UU, 00h, C}) ← (HL)
B ← B – 1
C ← C – 1
HL ← HL – 1
} while B ≠ 0
Description
The CPU loads the contents of the memory location specified by the multibyte HL register
into CPU memory. The CPU next outputs this byte to the I/O address specified by the C
register with the High byte of the address, ADDR[15:8], forced to 0. The upper byte of the
address bus, ADDR[23:16] is undefined for I/O addresses. The B, C, and HL registers are
decremented. The instruction repeats until register B equals 0.
Condition Bits Affected
Attributes
S Undefined.
Z Set if B – 1 = 0; reset otherwise.
H Undefined.
P/V Undefined.
N Set if msb of data is logical 1; reset otherwise.
C Undefined.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
OTDMR —X 2 + 3 * BED, 9B
OTDMR.S —1 3 + 3 * B52, ED, 9B
OTDMR.L —0 3 + 3 * B49, ED, 9B
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