ZiLOG eZ80 User Manual

eZ80
®
CPU
User Manual
UM007714-0908 CPU Instruction Set
261
OTDRX
Output to I/O and Decrement Memory Address with Stationary I/O Address
Operation
repeat {
{UU, DE[15:0]} ← (HL)
BC ← BC – 1
HL ← HL – 1
} while BC ≠ 0
Description
The CPU loads the contents of the memory location specified by the multibyte HL register
into CPU memory. The CPU next outputs this byte to the I/O address {UU, DE[15:0]}.
The upper byte of I/O addresses is undefined. The BC and HL registers decrement. The Z
Flag is set to 1 if the BC register decrements to 0. The instruction repeats until the BC reg-
ister equals 0.
Condition Bits Affected
Attributes
Note
This instruction is not supported on eZ80190 device.
S Not affected.
Z Set of BC – 1 = 0; reset otherwise.
H Not affected.
P/V Not affected.
N Set if msb of data is logical 1; reset otherwise.
C Not affected.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
OTDRX —X 2 + 3 *
BC
ED, CB
OTDRX.S —1 3 + 3 *
BC
52, ED, CB
OTDRX.L —0 3 + 3 *
BC
49, ED, CB

ZiLOG eZ80 Specifications

General

Brand	ZiLOG
Model	eZ80
Category	Computer Hardware
Language	English