ZiLOG eZ80 User Manual

eZ80
®
CPU
User Manual
UM007714-0908 CPU Instruction Set
262
OTI2R
Output to I/O and Increment with Repeat
Operation
repeat {
({UU, DE[15:0]}) ← (HL)
BC ← BC – 1
DE ← DE+1
HL ← HL+1
} while BC ≠ 0
Description
The CPU loads the contents of the memory location specified by the multibyte HL register
into CPU memory. The CPU next outputs this byte to I/O address {UU, DE[15:0]}. The
upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The BC reg-
ister decrements. The DE and HL registers increment. The instruction repeats until register
BC equals 0.
Condition Bits Affected
Attributes
Note
This instruction operates differently in eZ80190 device product. In the eZ80190, operation
is:
S Not affected.
Z Set if BC – 1 = 0; reset otherwise.
H Not affected.
P/V Not affected.
N Set if msb of data is logical 1; reset otherwise.
C Not affected.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
OTI2R —X 2 + 3 * BED, B4
OTI2R.S —1 3 + 3 * B52, ED, B4
OTI2R.L —0 3 + 3 * B49, ED, B4

ZiLOG eZ80 Specifications

General

Brand	ZiLOG
Model	eZ80
Category	Computer Hardware
Language	English