ZiLOG eZ80 User Manual

eZ80
®
CPU
User Manual
UM007714-0908 CPU Instruction Set
264
OTIM
Output to I/O and Increment
Operation
({UU, 00h,C}) ← (HL)
B ← B – 1
C ← C+1
HL ← HL+1
Description
The CPU loads the contents of the memory location specified by the multibyte HL register
into CPU memory. The CPU next outputs this byte to the I/O address specified by the C
register with the High byte of the address, ADDR[15:8], forced to 0. The upper byte of the
address bus, ADDR[23:16] is undefined for I/O addresses. The B register decrements. The
C and HL registers increment.
Condition Bits Affected
Attributes
S Undefined.
Z Set if B – 1 = 0; reset otherwise.
H Undefined.
P/V Undefined.
N Set if msb of data is logical 1; reset otherwise.
C Undefined.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
OTIM —X 5ED, 83
OTIM.S —1 652, ED, 83
OTIM.L —0 649, ED, 83

ZiLOG eZ80 Specifications

General

Brand	ZiLOG
Model	eZ80
Category	Computer Hardware
Language	English