EasyManuals Logo

ZiLOG eZ80 User Manual

Default Icon
411 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #274 background imageLoading...
Page #274 background image
eZ80
®
CPU
User Manual
UM007714-0908 CPU Instruction Set
265
OTIMR
Output to I/O and Increment
Operation
repeat {
({UU, 00h, C}) (HL)
B B – 1
C C+1
HL HL+1
} while B 0
Description
The CPU loads the contents of the memory location specified by the multibyte HL register
into CPU memory. The CPU next outputs this byte to the I/O address specified by the C
register with the High byte of the address, ADDR[15:8], forced to 0. The upper byte of the
address bus, ADDR[23:16] is undefined for I/O addresses. The B register decrements. The
C and HL registers increment. The instruction repeats until the B register equals 0.
Condition Bits Affected
Attributes
S Undefined.
Z Set if B – 1 = 0; reset otherwise.
H Undefined.
P/V Undefined.
N Set if msb of data is logical 1; reset otherwise.
C Undefined.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
OTIMR —X 2 + 3 * BED, 93
OTIMR.S —1 3 + 3 * B52, ED, 93
OTIMR.L —0 3 + 3 * B49, ED, 93

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the ZiLOG eZ80 and is the answer not in the manual?

ZiLOG eZ80 Specifications

General IconGeneral
BrandZiLOG
ModeleZ80
CategoryComputer Hardware
LanguageEnglish

Related product manuals