ZiLOG eZ80 User Manual

eZ80
®
CPU
User Manual
UM007714-0908 CPU Instruction Set
353
SRL (IX/Y+d)
Shift Right Logical
Operation
Description
The ( IX/Y + d ) operand is an 8-bit value at the memory location specified by the contents
of the Index Register, IX or IY, added to the two’s-complement displacement
d . The CPU
manipulates the contents of this memory location, (
IX/Y + d ), by shifting them right one bit
position. The CPU next copies the contents of bit 0 into the Carry Flag and resets bit 7.
Condition Bits Affected
Attributes
S Set if result is negative; reset otherwise.
Z Set if result is 0; reset otherwise.
H Reset.
P/V Set if parity is even; reset otherwise.
N Reset.
C Data from bit 0 of the source.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
SRL (IX+d)X 7 DD, CB, dd, 3E
SRL.S (IX+d)1 8 52, DD, CB, dd, 3E
SRL.L (IX+d)0 8 49, DD, CB, dd, 3E
SRL (IY+d)X 7 FD, CB, dd, 3E
SRL.S (IY+d)1 8 52, FD, CB, dd, 3E
SRL.L (IY+d)0 8 49, FD, CB, dd, 3E
C
7
0
(IX/Y+d)
0

ZiLOG eZ80 Specifications

General

Brand	ZiLOG
Model	eZ80
Category	Computer Hardware
Language	English