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ZiLOG eZ80 User Manual

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eZ80
®
CPU
User Manual
UM007714-0908 Memory Mode Switching
28
Because the CPU core resets to Z80 MEMORY mode, a
JP.LIL
Mmn
is recommended
for use near the beginning of source programs that run primarily in ADL MEMORY
mode.
JP Mmn 1 JP Mmn
assembles to
C3 nn mm MM
The starting program counter is PC[23:0]. Write the
3-byte immediate value {MM, mm, nn}, to
PC[23:0]. The ADL mode bit remains set to 1. The
ending program counter is PC[23:0] = {MM, mm,
nn}.
JP.LIL Mmn 1 JP.LIL Mmn
assembles to
5B C3 nn mm
MM
This operation is the same as the previous
operation. The .LIL extension does not affect
operation when beginning in ADL mode.
JP.SIS mn 1 JP.SIS mn
assembles to
40 C3 nn mm
The starting program counter is PC[23:0]. Write the
2-byte immediate value {mm, nn}, to PC[15:0].
Reset the ADL mode bit to 0. The ending program
counter is {MBASE, PC[15:0]} = {MBASE, mm, nn}.
JP.SIL
Mmn
1 N/A An illegal suffix for this instruction.
JP.LIS mn 1 N/A An illegal suffix for this instruction.
Table 16. JP (rr) Instruction
User Code
ADL
Mode
Assembled
Code Operation
JP (rr) 0 JP (rr)
assembles to
E9 or DD/FD
E9
The starting program counter is {MBASE,
PC[15:0]}. Write the 2-byte value stored in rr[15:0]
to PC[15:0]. The ADL mode bit remains cleared to
0. The ending program counter is {MBASE,
PC[15:0]} = {MBASE, rr[15:0]}.
JP.S (rr) 0 JP.SIS (rr)
assembles to
40 E9 or 40
DD/FD E9
This operation is the same as the previous
operation. The .SIS extension does not affect
operation when beginning in Z80 mode.
JP.L (rr) 0 JP.LIS (rr)
assembles to
49 E9 or
49 DD/FD E9
The starting program counter is {MBASE,
PC[15:0]}. Write the 3-byte value stored in rr[23:0]
to PC[23:0]. Set the ADL mode bit to 1. The ending
program counter is PC[23:0] = rr[23:0].
Table 15. JP Mmn Instruction (Continued)
User Code
ADL
Mode
Assembled
Code Operation
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ZiLOG eZ80 Specifications

General IconGeneral
CPU FamilyeZ80
CoreeZ80
Architecture8-bit
Clock Speedup to 50 MHz
Addressable Memory16 MB
Register Size8-bit
Serial InterfacesUART, SPI, I2C
Operating Temperature-40°C to +85°C
Instruction SetZ80 compatible
On-Chip Flash MemoryUp to 256 KB
On-Chip SRAMUp to 16 KB
Operating Voltage3.0V to 3.6V
Package TypesLQFP, QFP
TimersMultiple timers/counters
Power ConsumptionLow power

Summary

Introduction

Architectural Overview

Memory Modes

Z80 MEMORY Mode

Describes Z80-compatible addressing with 16-bit registers and default operating mode on reset.

ADL MEMORY Mode

Explains ADL mode utilizing 16MB linear addressing and 24-bit registers.

Registers and Bit Flags

eZ80® CPU Working Registers

Details the two banks of working registers: main and alternate.

eZ80® CPU Control Register Definitions

Lists registers controlling CPU operation: I, IX, IY, MBASE.

eZ80® CPU Registers in Z80 Mode

Details CPU registers and bit flags when operating in Z80 mode.

Memory Mode Switching

Mixed-Memory Mode Applications

Interrupts

eZ80® CPU Response to a Nonmaskable Interrupt

Details how the CPU accepts and responds to nonmaskable interrupts (NMIs).

eZ80® CPU Response to a Maskable Interrupt

Describes how the CPU responds to maskable interrupts using Interrupt Modes 0, 1, and 2.

I/O Space

Addressing Modes

CPU Instruction Set

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