ZiLOG eZ80 User Manual

eZ80
®
CPU
User Manual
UM007714-0908 Interrupts
41
Interrupt Mode 2
In Interrupt Mode 2, when an interrupt is accepted, the interrupting device places the
lower eight bits of the interrupt vector on the data bus, D[7:0], during the interrupt
acknowledge cycle. Bit 0 of this byte must be 0. The middle byte of the interrupt vector
address is set by the CPU’s Interrupt Vector Register, I.
In applications that run Z80 mode code exclusively, the interrupt vector address is
{MBASE, I[7:0], D[7:0]}. A 16-bit word is fetched from the interrupt vector address and
loaded into the lower two bytes of the Program Counter, PC[15:0].
In mixed-memory mode applications or ADL mode applications, the interrupt vector
address is { I[15:0], D[7:0]}. A 24-bit word is fetched from the interrupt vector address
and loaded into the Program Counter, PC[23:0].
Z80 mode 0 1 IEF1 ← 0
IEF2 ← 0
The starting program counter is {MBASE, PC[15:0]}.
Push the 2-byte return address, PC[15:0], onto the
SPL stack. Push a 02h byte onto the SPL stack,
indicating interrupting from Z80 mode (because
ADL = 0). Set the ADL mode bit to 1. Write 000038h to
PC[23:0]. The ending program counter is
PC[23:0] = 000038h. The interrupt service routine must
end with RETI.L.
ADL mode 1 1
IEF1 ← 0
IEF2 ← 0
The starting program counter is PC[23:0]. Push the 3-
byte return address, PC[23:0], onto the SPL stack.
Push a 03h byte onto the SPL stack, indicating an
interrupt from ADL mode (because ADL = 1). The ADL
mode bit remains set to 1. Write 000038h to PC[23:0].
The ending program counter is PC[23:0] = 000038h.
The interrupt service routine must end with RETI.L
Table 23. Interrupt Mode 1 Operation (Continued)
Current
Memory Mode
ADL
Mode
Bit
MADL
Control
Bit Operation

ZiLOG eZ80 Specifications

General

CPU Family	eZ80
Core	eZ80
Architecture	8-bit
Clock Speed	up to 50 MHz
Addressable Memory	16 MB
Register Size	8-bit
Serial Interfaces	UART, SPI, I2C
Operating Temperature	-40°C to +85°C
Instruction Set	Z80 compatible
On-Chip Flash Memory	Up to 256 KB
On-Chip SRAM	Up to 16 KB
Operating Voltage	3.0V to 3.6V
Package Types	LQFP, QFP
Timers	Multiple timers/counters
Power Consumption	Low power

Summary

Introduction

Architectural Overview

Processor Description

Pipeline Description

Memory Modes

Z80 MEMORY Mode

Describes Z80-compatible addressing with 16-bit registers and default operating mode on reset.

ADL MEMORY Mode

Explains ADL mode utilizing 16MB linear addressing and 24-bit registers.

Registers and Bit Flags

eZ80® CPU Working Registers

Details the two banks of working registers: main and alternate.

eZ80® CPU Control Register Definitions

Lists registers controlling CPU operation: I, IX, IY, MBASE.

eZ80® CPU Control Bits

eZ80® CPU Registers in Z80 Mode

Details CPU registers and bit flags when operating in Z80 mode.

Memory Mode Switching

ADL Mode and Z80 Mode

Opcode Suffixes for Memory Mode Control

Mixed-Memory Mode Applications

MIXED MEMORY Mode Guidelines

Interrupts

Interrupt Enable Flags (IEF1 and IEF2)

Interrupts in Mixed Memory Mode Applications

eZ80® CPU Response to a Nonmaskable Interrupt

Details how the CPU accepts and responds to nonmaskable interrupts (NMIs).

eZ80® CPU Response to a Maskable Interrupt

Describes how the CPU responds to maskable interrupts using Interrupt Modes 0, 1, and 2.

I/O Space

Addressing Modes

Register Indirect Addressing

CPU Instruction Set

eZ80® CPU Assembly Language Programming Introduction

eZ80® CPU Instruction Notations