ZiLOG eZ80 User Manual

eZ80
®
CPU
User Manual
UM007714-0908 Interrupts
41
Interrupt Mode 2
In Interrupt Mode 2, when an interrupt is accepted, the interrupting device places the
lower eight bits of the interrupt vector on the data bus, D[7:0], during the interrupt
acknowledge cycle. Bit 0 of this byte must be 0. The middle byte of the interrupt vector
address is set by the CPU’s Interrupt Vector Register, I.
In applications that run Z80 mode code exclusively, the interrupt vector address is
{MBASE, I[7:0], D[7:0]}. A 16-bit word is fetched from the interrupt vector address and
loaded into the lower two bytes of the Program Counter, PC[15:0].
In mixed-memory mode applications or ADL mode applications, the interrupt vector
address is { I[15:0], D[7:0]}. A 24-bit word is fetched from the interrupt vector address
and loaded into the Program Counter, PC[23:0].
Z80 mode 0 1 IEF1 ← 0
IEF2 ← 0
The starting program counter is {MBASE, PC[15:0]}.
Push the 2-byte return address, PC[15:0], onto the
SPL stack. Push a 02h byte onto the SPL stack,
indicating interrupting from Z80 mode (because
ADL = 0). Set the ADL mode bit to 1. Write 000038h to
PC[23:0]. The ending program counter is
PC[23:0] = 000038h. The interrupt service routine must
end with RETI.L.
ADL mode 1 1
IEF1 ← 0
IEF2 ← 0
The starting program counter is PC[23:0]. Push the 3-
byte return address, PC[23:0], onto the SPL stack.
Push a 03h byte onto the SPL stack, indicating an
interrupt from ADL mode (because ADL = 1). The ADL
mode bit remains set to 1. Write 000038h to PC[23:0].
The ending program counter is PC[23:0] = 000038h.
The interrupt service routine must end with RETI.L
Table 23. Interrupt Mode 1 Operation (Continued)
Current
Memory Mode
ADL
Mode
Bit
MADL
Control
Bit Operation

ZiLOG eZ80 Specifications

General

Brand	ZiLOG
Model	eZ80
Category	Computer Hardware
Language	English