ZiLOG eZ80 User Manual

eZ80
®
CPU
User Manual
UM007714-0908 CPU Instruction Set
62
EX AF,AF’
AF ↔
AF’
08 ******
EX DE,HL
DE ↔
HL
EB ——————
EX (SP),ss
(SP) ↔
ss
HL E3 ——————
IX/Y DD/FD E3
EXX
BC ↔
BC’
DE ↔ DE’
HL ↔ HL’
D9 ——————
HALT 76 ——————
IM n ED 46–5E ——————
IN A,(n)
A ←(
{00h, A, n)})
DB ——————
IN r,(BC) also IN r,(C)
r
← ({00h, BC[15:0]})
ED 40–78 **0 P 0–
IN0 r,(n)
r
← ({0000h, n})
ED 00–38 **0 P 0–
INC ss
ss
← ss +1
(HL) 34 *** V 1–
ir DD/FD 24–2C *** V 1–
IX/Y DD/FD 23 ——————
(IX/Y+d) DD/FD 34 dd *** V 1–
r 04–3C *** V 1–
rr 03–23 ——————
SP 33 ——————
IND
(HL)
← ({00h, BC[15:0]})
B
← B – 1
HL
← HL – 1
ED AA —*—— *—
Table 37. Instruction Summary (Continued)
Instruction and Operation
Address Mode
Opcode(s)
(Hex)
Flags Affected
Dest Source S Z H P/V N C
Note: *This flag value is a function of the result of the affected operation.
— = No Change.
0 = Set to 0.
1 = Set to 1.
V = Set to 1 if overflow occurs.
X = Undetermined.
P = Set to the parity of the result (0 if odd parity, 1 if even parity).
IEF2 = The value of Interrupt Enable Flag 2.

ZiLOG eZ80 Specifications

General

Brand	ZiLOG
Model	eZ80
Category	Computer Hardware
Language	English