ZiLOG eZ80

eZ80
®
CPU
User Manual
UM007714-0908 CPU Instruction Set
61
CPI
A–(HL)
HL ←
HL+1
BC ←
BC – 1
ED A1 ****1—
CPIR
repeat {
A–(HL)
HL ←
HL+1
BC ←
BC – 1
} while (~Z and BC
≠ 0)
ED B1 ****1—
CPL
A ←
~A
2F —— 1 — 1 —
DAA
A ←
decimal adjust (A)
27 *** P—*
DEC ss
ss
← ss – 1
(HL) 35 *** V 1—
ir DD/FD 25–2D *** V 1—
IX/Y DD/FD 2B ——————
(IX/Y+d) DD/FD 35 dd *** V 1—
r 05–3D *** V 1—
rr 0B–2B ——————
SP 3B ——————
DI
IEF1,2
← 0
F3 ——————
DJNZ d
B
← B – 1
if B ≠ 0 {
PC
← PC+ d
}
10 dd ——————
EI
IEF1,2
← 1
FB ——————
Table 37. Instruction Summary (Continued)
Instruction and Operation
Address Mode
Opcode(s)
(Hex)
Flags Affected
Dest Source S Z H P/V N C
Note: *This flag value is a function of the result of the affected operation.
— = No Change.
0 = Set to 0.
1 = Set to 1.
V = Set to 1 if overflow occurs.
X = Undetermined.
P = Set to the parity of the result (0 if odd parity, 1 if even parity).
IEF2 = The value of Interrupt Enable Flag 2.