ZiLOG eZ80 User Manual

eZ80
®
CPU
User Manual
UM007714-0908 CPU Instruction Set
67
LD (IX/Y+d), ss
(IX/Y+d)
← ss
IX/Y DD/FD 3E-3F ——————
n DD/FD 36
r DD/FD 70-77
rr DD/FD 0F–2F
LD MB,A
if ADL mode {MBASE
← A}
ED 6D ——————
LD (Mmn), ss
(Mmn)
← ss
A 32 ——————
IX/Y DD/FD 22
rr ED 43–63
SP ED 73
LD R, A
R
← A
A ED 4F ——————
LD r, s
r
← s
(HL) 46-7E ——————
ir DDFD 44-7D
(IX/Y+d) DD/FD 46-7E
n 06-3E
r’ 41-7F
LD rr, ss
rr
← ss
(HL) ED 07-27 ——————
(IX/Y+d) DD/FD 07-27
Mmn 01-21
(Mmn) ED 4B-6B
LD (rr), A
(rr)
← A
A 02, 12, 77 ——————
LD SP, ss
SP
← ss
HL F9 ——————
IX/Y DD/FD F9
Mmn 31
(Mmn) ED 7B
Table 37. Instruction Summary (Continued)
Instruction and Operation
Address Mode
Opcode(s)
(Hex)
Flags Affected
Dest Source S Z H P/V N C
Note: *This flag value is a function of the result of the affected operation.
— = No Change.
0 = Set to 0.
1 = Set to 1.
V = Set to 1 if overflow occurs.
X = Undetermined.
P = Set to the parity of the result (0 if odd parity, 1 if even parity).
IEF2 = The value of Interrupt Enable Flag 2.

ZiLOG eZ80 Specifications

General

Brand	ZiLOG
Model	eZ80
Category	Computer Hardware
Language	English