Advantech AIMB-784

39 AIMB-784 User Manual
Chapter 3 BIOS Operation
 Adjacent Cache Line Prefetch
The Adjacent Cache-Line Prefetch mechanism, like automatic hardware
prefetch, operates without programmer intervention. When it is enabled through
the BIOS, two 64-byte cache lines are fetched into a 128-byte sector, regardless
of whether the additional cache line has been requested or not. You may choose
to "Enable or Disable" it.
 EIST
Enable or Disable Intel SpeedStep.
 CPU C states
Intel C states setting for power saving.
 Package C State limit
To select Package C State limit: C0/C1, C2, C3, C6, C7, C7s, or AUTO
 Intel TXT(LT) Support
Enable or Disable Intel TXT support.
 ACPI T State
Enable or Disable ACPI T state support
3.2.2.6 SATA Configuration
Figure 3.10 SATA Configuration
 SATA Controller(s)
"Enable or Disable" SATA Controller
 SATA Mode Selection
This can be configured as IDE, RAID or AHCI.