OV (pin 12): This open collector output pin goes High when
STATUS SELECT (pin 11) is Low and the OV SENSE (pin
13) is Low. The Low state of pin 13 indicates an overvoltage
condition. OV is open-circuited when STATUS SELECT is
High.
OV SENSE (pin 13): When an overvoltage occurs (pin 9 on
the power module goes Low), this input pin goes Low
which causes OV (pin 12) to go High when STATUS
SELECT (pin 11) is Low.
THERM (pin 14): This input signal, when Low (indicating
an overtemperature condition), causes OT (pin 15) to go
High when STATUS SELECT (pin 11) is Low.
OT (pin 15): This open collector output signal goes High
when both the STATUS SELECT (pin 11) and THERM (pin
14) inputs are Low indicating an OT (overtemperature)
condition. OT is open-circuited when STATUS SELECT is
High.
- CL LOOP (pin 16): This input signal, when Low, indicates
that the supply's output is in negative current limit. Figure
4-19 shows how this signal is decoded causing -CLO (pin
10) to go Low.
-7.00 V (pin 17): The - 7.00 V bias voltage can range from -
7.42 V to - 6.48 V.
+ CLO (pin 18): This open-collector output signal takes on
the state of the internal +CC flip-flop when STATUS
SELECT (pin 11) is Low. Figure 4-19 shows the conditions
that cause + CLO to be Low. The + CC mode is indicated
when + CLO is Low. +CLO is open-circuited when STATUS
SELECT is High.
CVO (pin 19): This open collector output signal takes on the
state of the internal CV flip-flop when STATUS SELECT is
Low. Figure 4-19 shows the conditions that cause CVO to go
Low. The CV mode is indicated when CVO is Low. CVO is
open-circuited when STATUS SELECT is High.
+ CL LOOP (pin 20): This input signal, when High,
indicates that the supply's output is in the positive current
limit. Figure 4-19 shows how this signal is decoded causing
+ CLO (pin 18) to go Low.
CV LOOP (pin 21): When the supply's output is in the CV
mode, the voltage level of this input signal should fall
within the "medium" level (see Table 4-16). A High level at
pin 21 indicates that the output is unregulated. Figure 4-19
shows how the CV LOOP signal is decoded causing CVO
(pin 19) to go Low.
Common (pin 22): Along with pin 5, this is a common
return for the bias supplies.
DELAY CAP (pin 23): When BIAS TRIP (pin 27) is High,
this signal causes a slow charge of an external delay
capacitor toward the DELAY CAP High level which, when
reached, causes PCLR (pin 26) to go High. When BIAS TRIP
is Low, this signal causes a quick discharge of the external
delay capacitor (see Figure 4-18).
OUTPUT ENABLE (pin 24): After PCLR (pin 26) goes High
and the power supply passes its self test, the microcomputer
U312 causes this pin to go Low. With PCLR High and
OUTPUT ENABLE Low, ON/OFF (pin 25) goes High
enabling the output. With OUT ENABLE High, ON/OFF is
Low and the output will not supply power.
ON/OFF (pin 25): This output pin goes High when PCLR
(pin 26) is High and OUTPUT ENABLE (pin 24) is Low (see
Figure 4-18). When High, the ON/OFF line enables the
control circuits and current sources of the output board
which allows power to reach the output terminals.
PCLR (pin 26): This output goes High when DELAY CAP
(pin 23) goes High (see Figure 4-18). When PCLR is High
and OUTPUT ENABLE (pin 24) is Low, ON/OFF (pin 25)
goes High.
BIAS TRIP (pin 27): See DELAY CAP (pin 23) description.
Note that BIAS TRIP goes High when both the unregulated
bias supply voltage and the medium rail voltage are high
enough.
15 V (pin 28): The -15 V bias voltage can range from 15.55 V
to -13.98 V.
4-32 Troubleshooting Status Problems. An output will
report its operating status (CV, + CC, - CC, OV, OT, and
UNR) when queried to do so (see paragraph 5-25 in the
Operating Manual). The front panel also indicates the
present status of the output. When an output appears to
operate properly but incorrect or multiple status is reported,
the problem may be caused by the status monitor circuit
section of U327, microcomputer U312, or a short on the data
lines between these two IC's. Note, however, that certain
load transients can cause a temporary multiple status
condition to exist and this is not to be considered a problem.
A status decoding table, which indicates the logic
relationship between the five status input lines and the six
status output lines, is included in Figure 4-19. To
troubleshoot status problem, set up an oscilloscope as
4-52
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