Publication 1762-RM001C-EN-P
C-10 System Status File
Math Overflow Selection
Set (1) this bit when you intend to use 32-bit addition and subtraction.
When S:2/14 is set, and the result of an ADD, SUB, MUL, or DIV
instruction cannot be represented in the destination address (underflow or
overflow),
•
the overflow bit S:0/1 is set,
•
the overflow trap bit S:5/0 is set,
•
and the destination address contains the unsigned truncated least
significant 16 or 32 bits of the result.
The default condition of S:2/14 is cleared (0). When S:2/14 is cleared (0),
and the result of an ADD, SUB, MUL, or DIV instruction cannot be
represented in the destination address (underflow or overflow),
•
the overflow bit S:0/1 is set,
•
the overflow trap bit S:5/0 is set,
•
the destination address contains +32,767 (word) or +2,147,483,647
(long word) if the result is positive; or -32,768 (word) or
-2,147,483,648 (long word) if the result is negative.
To provide protection from inadvertent alteration of your selection,
program an unconditional OTL instruction at address S:2/14 to ensure the
new math overflow operation. Program an unconditional OTU instruction
at address S:2/14 to ensure the original math overflow operation.
Watchdog Scan Time
This byte value contains the number of 10 ms intervals allowed to occur
during a program cycle. The timing accuracy is from -10 ms to +0 ms. This
means that a value of 2 results in a timeout between 10 and 20 ms.
If the program scan time value equals the watchdog value, a watchdog
major error is generated (code 0022H).
Free Running Clock
This register contains a free running counter that is incremented every 100
µs. This word is cleared (0) upon entering an executing mode.
Address Data Format Range Type User Program Access
S:2/14 binary 0 or 1 control read/write
Address Data Format Range Type User Program Access
S:3H Byte 2 to 255 control read/write
Address Data Format Range Type User Program Access
S:4 binary 0 to FFFF status read/write
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