Publication 1762-RM001C-EN-P
Using the High-Speed Counter 5-11
High Preset Mask (HPM)
The HPM (High Preset Mask) control bit is used to enable (allow) or
disable (not allow) a high preset interrupt from occurring. If this bit is
clear (0), and a High Preset Reached condition is detected by the HSC, the
HSC user interrupt is not executed.
This bit is controlled by the user program and retains its value through a
power cycle. It is up to the user program to set and clear this bit.
High Preset Interrupt (HPI)
The HPI (High Preset Interrupt) status bit is set (1) when the HSC
accumulator reaches the high preset value and the HSC interrupt is
triggered. This bit can be used in the control program to identify that the
high preset condition caused the HSC interrupt. If the control program
needs to perform any specific control action based on the high preset, this
bit is used as conditional logic.
This bit can be cleared (0) by the control program and is also cleared by
the HSC sub-system whenever these conditions are detected:
•
Low Preset Interrupt executes
•
Underflow Interrupt executes
•
Overflow Interrupt executes
•
Controller enters an executing mode
Description Address Data Format
HSC Modes
(1)
(1) For Mode descriptions, see HSC Mode (MOD) on page 5-16.
Type User Program Access
HPM - High
Preset Mask
HSC:0/HPM bit 0 to 7 control read/write
Description Address Data Format
HSC Modes
(1)
(1) For Mode descriptions, see HSC Mode (MOD) on page 5-16.
Type User Program Access
HPI - High
Preset Interrupt
HSC:0/HPI bit 0 to 7 status read/write
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