Publication 1762-RM001C-EN-P
5-14 Using the High-Speed Counter
Overflow Mask (OFM)
The OFM (Overflow Mask) control bit is used to enable (allow) or disable
(not allow) an overflow interrupt from occurring. If this bit is clear (0),
and an overflow reached condition is detected by the HSC, the HSC user
interrupt is not executed.
This bit is controlled by the user program and retains its value through a
power cycle. It is up to the user program to set and clear this bit.
Overflow Interrupt (OFI)
The OFI (Overflow Interrupt) status bit is set (1) when the HSC
accumulator counts through the overflow value and the HSC interrupt is
triggered. This bit can be used in the control program to identify that the
overflow variable caused the HSC interrupt. If the control program needs
to perform any specific control action based on the overflow, this bit is
used as conditional logic.
This bit can be cleared (0) by the control program and is also cleared by
the HSC sub-system whenever these conditions are detected:
•
Low Preset Interrupt executes
•
High Preset Interrupt executes
•
Underflow Interrupt executes
•
Controller enters an executing mode
Description Address Data Format
HSC Modes
(1)
(1) For Mode descriptions, see HSC Mode (MOD) on page 5-16.
Type User Program Access
OFM - Overflow
Mask
HSC:0/OFM bit 0 to 7 control read/write
Description Address Data Format
HSC Modes
(1)
(1) For Mode descriptions, see HSC Mode (MOD) on page 5-16.
Type User Program Access
OFI - Overflow
Interrupt
HSC:0/OFI bit 0 to 7 status read/write
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