Altera DE2 Board - Page 38

Using the System
35
Figure 3.17 SDRAM, SRAM, Flash Memory on DE2
Signal Name FPGA Pin No.
Description
DRAM_ADDR[0]
PIN_T6 SDRAM Address[0]
DRAM_ADDR[1]
PIN_V4 SDRAM Address[1]
DRAM_ADDR[2]
PIN_V3 SDRAM Address[2]
DRAM_ADDR[3]
PIN_W2 SDRAM Address[3]
DRAM_ADDR[4]
PIN_W1 SDRAM Address[4]
DRAM_ADDR[5]
PIN_U6 SDRAM Address[5]
DRAM_ADDR[6]
PIN_U7 SDRAM Address[6]
DRAM_ADDR[7]
PIN_U5 SDRAM Address[7]
DRAM_ADDR[8]
PIN_W4 SDRAM Address[8]
DRAM_ADDR[9]
PIN_W3 SDRAM Address[9]
DRAM_ADDR[10]
PIN_Y1 SDRAM Address[10]
DRAM_ADDR[11]
PIN_V5 SDRAM Address[11]
DRAM_DQ[0] PIN_V6 SDRAM Data[0]
DRAM_DQ[1] PIN_AA2 SDRAM Data[1]
DRAM_DQ[2] PIN_AA1 SDRAM Data[2]
DRAM_DQ[3] PIN_Y3 SDRAM Data[3]
DRAM_DQ[4] PIN_Y4 SDRAM Data[4]
DRAM_DQ[5] PIN_R8 SDRAM Data[5]
DRAM_DQ[6] PIN_T8 SDRAM Data[6]
DRAM_DQ[7] PIN_V7 SDRAM Data[7]
DRAM_DQ[8] PIN_W6 SDRAM Data[8]
DRAM_DQ[9] PIN_AB2 SDRAM Data[9]
DRAM_DQ[10] PIN_AB1 SDRAM Data[10]
DRAM_DQ[11] PIN_AA4 SDRAM Data[11]