3 CPU Core Information 13
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
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TMR0CON.7
IIS_CON2.3&IIS_CON2.1
RTCON.7
UARTSTA.5&UARTSTA.4
IP0.7
LVDCON.7
IIS_CON2.3&IIS_CON2.2&
IIS_CON2.1&IIS_CON2.0
3.4.2 Interrupt Priority
There are 4 levels of interrupt priority: Level 3 to 0. All interrupts have individual priority bits in the interrupt priority
registers to allow each interrupt to be assigned a priority level from 3 to 0. All interrupts also have a natural hierarchy.
In this manner, when a set of interrupts has been assigned the same priority, a second hierarchy determines which
interrupt is allowed to take precedence. The natural hierarchy is determined by analyzing potential interrupts in a
sequential manner with the order listed in Table 3-2.
The processor indicates that an interrupt condition occurred by setting the respective flag bit. This bit is set
regardless of whether the interrupt is enabled or disabled.
3.5 Special Function Register Mapping (SFR)
Table 3-3 Special function registers naming and address
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