APPOTECH CW6632B - CPU and Memory Related SFR Description

3 CPU Core Information 15
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
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7
6
5
4
3
2
1
0
7820H
P2DRV0
P1DRV0
P0DRV0
IIS_WSCNT
SPIBAUD
SPIDMACNT
SPIDMAPTRH
SPIDMAPTRL
7818H
CRCRES1
CRCRES0
IIS_BCLK_CFG
UARTDIV
UARTDMATXC
NT
UARTDMARXC
NT
UARTDMATXP
TR
UARTDMARXP
TR
7810H
UART1STA
UART1DATA
UART1BAUD
UART1CON
HFMPTRH
HFMPTRL
BFEPTRH
BFEPTRL
7808H
IRTADT3
IRDAT2
IRDAT1
IRDAT0
IIS_VALBIT
SPMODE1
PIE1
PWRCON2
7800H
PWRCON1
RC_TRIM
IIS_ADR1
RC_TEST
SDDPTR
SDDCNT
SDCPTR
SDBAUD
3.7 CPU and Memory related SFR Description
Register 3-1 DPCON – Data Pointer Configure Register
Position
7
6
5
4
3
2
1
0
Name
IA
DPID0
DPID1
DPAID
DPTSL
EINSTEN
DPSEL
Default
1
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IA: Select Interrupt Vector‟s Base Address
00 = Base address is 0x0003
01 = Base address is 0x4003
10 = Base address is 0x8003
11 = Base address is 0xc003
note：interrupt address is determined by SPMODE1[4]
0 = interrupt base address depend on IA
1 = interrupt base address is 0x2000
DPID0: DPTR0 increase direction control
0 = DPTR increase
1 = DPTR decrease
DPID1: DPTR1 increase direction control
0 = DPTR increase
1 = DPTR decrease
DPAID: DPTR auto increment enables
0 = Auto increment disable
1 = Auto increment enable
DPTSL: DPSEL toggle enable
0 = DPSEL toggle disable
1 = DPSEL toggle enable
EINSTEN: Extern instruction enables
0 = Disable
1 = Enable