APPOTECH CW6632B - Page 22

16 3.7 CPU and Memory related SFR Description
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
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DPSEL: DPTR Select
0 = Active DPTR0
1 = Active DPTR1
Data Pointer Register is an 16-bit address pointer，it can split up into two register，DPL and DPH. Data pointer
register always used as indirect addressing register.
Note：interrupt address is determined by SPMODE1[4]
Register 3-2 DPL0 – Data Pointer Low Byte
Position
7
6
5
4
3
2
1
0
Name
DPL0
Default
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Register 3-3 DPL1 – Data Pointer Low Byte
Position
7
6
5
4
3
2
1
0
Name
DPL1
Default
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Register 3-4 DPH0 – Data Pointer High Byte
Position
7
6
5
4
3
2
1
0
Name
DPH0
Default
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Register 3-5 DPH1 – Data Pointer High Byte
Position
7
6
5
4
3
2
1
0
Name
DPH1
Default
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The data pointers (DPTR0 and DPTR1) are used to assign a memory address for the MOVX instructions. This
address can point to a MOVX RAM location. Two pointers are useful when moving data from one memory area to
another. The user can select the active pointer through a dedicated SFR bit (DPSEL: DPCON.0), or can activate an
automatic toggling feature for altering the pointer selection (DPTSL: DPCON.2). An additional feature, if selected,
provides automatic incrementing or decrementing of the current DPTR.
Data pointer increment/decrement bits DPID0 (DPCON.5) and DPID1 (DPCON.4) define how the INC DPTR
instruction functions in relation to the active DPTR.
The CW6632B offers a programmable option that allows any instructions related to data pointer to toggle the DPSEL
bit automatically. This option is enabled by setting the toggle-select-enable bit (DPTSL) to logic 1.
Once enabled, the DPSEL bit is automatically toggled after the execution of one of the following 5 DPTR related
instructions:
MOVC A, @A+DPTR