Common Features Description
Atmel 8051 Microcontrollers Hardware Manual 2-72
4316B–8051–02/04
Figure 2-4. 80C51 Port Bit Latches and I/O Buffers.
As shown in Figure 2-4, the output drivers of Ports 0 and 2 are switchable to an internal
ADDR and ADDR/DATA bus by an internal CONTROL signal for use in external mem-
ory accesses. During external memory accesses, the P2 SFR remains unchanged, but
the P0 SFR gets 1s written to it.
Also shown in Figure 2-4, is that if a P3 bit latch contains a 1, then the output level is
controlled by the signal labeled “alternate output function.” The actual P3.X pin level is
always available to the pin’s alternate input function, if any.
Ports 1, 2, and 3 have internal pull-ups. Ports 0 has open-drain outputs. Each I/O line
can be independently used as an input or an output. (Ports 0 and 2 may not be used as
general purpose I/O when being used as the ADDR/DATA BUS). To be used as an
input, the port bit latch must contain a 1, which turns off the output driver FET. Then, for
Ports 1, 2, and 3, the pin is pulled high by the internal pull-up, but can be pulled low by
an external source.
Port 0 differs in not having internal pull-ups. The pull-up FET in the P0 output driver (see
Figure 2-4A) is used only when the Port is emitting 1’s during external memory
accesses. Otherwise the pull-up FET is off. Consequently P0 lines that are being used
as output port lines are open drain. Writing a 1 to the bit latch leaves both output FETs
off, so the pin floats. In that conditions it can be used as a high-impedance input.
Because Ports 1, 2, and 3 have fixed internal pull-ups they are sometimes called “quasi-
bidirectional” ports. When configured as inputs they pull high and will source current (IIL,
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