Baumer VEXG - IO Circuits VEXG; IO Circuits VEXU

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8.4.1.2 CongurableOutputs
With this feature, Baumer gives you the option to wire the output connectors to internal
signals that are controlled on the software side.
Signals
Off
ExposureActive
Signals
(Output) Line 1
state high
state low
IO Matrix
state selection
(software side)
signal selection
(software side)
8.4.2 IO Circuits VEXG
Input
Output
Pin 2
(IN1)
FPGA
FPGA
Pin 3
(GND)
Pin 1
(Power VCC)
Pin 4
(OUT)
R
L
(+12 ... 24 VDC ± 20 %)
Pin 3
(GND)
8.4.3 IO Circuits VEXU
Input
Output
Pin 2
(IN1)
FPGA
FPGA
Pin 3
(GND)
Pin 1
(Power IO)
Pin 4
(OUT)
R
L
(+5 ... 20 VDC ± 20 %)
Pin 3
(GND)
Figure31►
IO matrix