Brother HL-5130 - Main PCB Block Diagram

CHAPTER 3 THEORY OF OPERATION
3-2
1.2 Main PCB Block Diagram
Fig. 3-2 shows the block diagram of the main PCB. (HL-5130/5140/5150D/5170DN)
Reset Circuit
Program + Font ROM
HL-5130:2MB
HL-5140:4MB
HL-5150D/5170DN:8MB
RAM
HL-5130:8MB
HL-5140/5150D:16MB
HL-5170DN:32MB
RAM (DIMM)
(max. 128MB)
Option for HL-5140/5150D/5170DN
EEPROM
HL-5130/5140/5150D:512 x 8 bit
HL-5170DN:8192 x 8 bit
CPU Core
(SPARClite 133MHz)
A S I C
Oscillator 66.6MHz
Address Decoder
DRAM Control
Timer
FIFO
CDCC Parallel I/O
Soft Support
EEPROM I/O
Engine Control I/O
To Engine PCB
BUS
INT
To PC
USB I/O
To PC
Network Program
(HL-5170DN only)(1.5 MB)
STRAGE (0.5 MB)
PCI Bus Control
Network Controller
To PC
or Hub
(HL-5170DN only)
Oscillator 12MHz
Oscillator 25MHz
(HL-5170DN only)
Fig. 3-2