33
4.2. Circuit Diagram
4.2.1. Main
To U14 IC(74HC670) Pin#3
From CPU P1.1
IC 74HC670 Pin#14,WA
GND
To VFD Driver STB
C15
0.1u
INT CLK (TO A/D)
C32
0.1u
C16
18pF
R18
0.5%
10K
R2
10K
0.5%
CON1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
U5
24C16N
1
2
3
4 5
6
7
8
A0
A1
A2
VSS SDA
SCL
WP
VDD
6100-PPD-2000-A
VDD
1
IC 74HC670 Pin#12,GW
Display Con 2
CON9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
C17
18pF
To U15 IC(74HC670) Pin#3
To VFD Driver CLK
CAL
To ECR (Out of range, CON 7 Pin#21)
R3~5,14~16
To VFD Driver DIN
C19
0.1u
uPD789177
uPD789177
34
35
36
38
39
40
41
42
19
18
16
33
32
31
30
21
20
1
2
3
4
5
6
7
8
27
26
24
23
13
12
25
10
11
22
9
28
37
43
29
17
44
14
15
P02
P03
P04
P05
P50
P51
P52
P53
P22/SI20/RxD20
P21/SO20/TxD20
P20/SCK20/ASCK20
P01
P00
P26/TO80
P25/TO80/SS20
P24/SDA0
P23/SCL0
P60/AN10
P61/AN11
P62/AN12
P63/AN13
P64/AN14
P65/AN15
P66/AN16
P67/AN17
X1
X2
XT1
XT2
P31/INTP1/TO81
P30/INTP0/TI81/CPT90
RESET
P10
P11
IC0(Vpp)
AVss
Vsso
Vss1
AVdd
Vddo
Vdd1
AVref
P32/INTP21/TO90
P33/INTP3/TO82/BZO90
R6
100k
0.5%
Vpp
VDD
To Q1
VDD
IC 74HC670 Pin#13,WB
10
/RESET
C5
0.1u
+
C31
100u
To ECR (Motion,Pin#13)
C18
0.1u
VDD
8 Vpp
To U14 IC(74HC670) Pin#1
R17
0.5%
10K
R7
10k
R11
0.5%100k
R9
0.5%
10k
6
R13
0.5%
10k
Connect CPU Pin#22 (IC <Vpp>)
To U14 IC(74HC670) Pin#15
VDD
7
4
VDD
Q1
1504
C33
0.1u
2
JP3
First Drawing H.J
MAIN CIRCUIT (uPD789177) For VFD
Custom
11Tuesday, August 12, 2003
Title
Size Document Number Rev
Date: Sheet of
C14
0.1u
9
VDD
XTAL
5.0MHz
3
To U15 IC(74HC670) Pin#1
To U15 IC(74HC670) Pin#15
5
To U15 IC(74HC670) Pin#2
CON 5
VDD
To U14 IC(74HC670) Pin#2
CON10
U3
KIA7045F
2 1
3
21
3
Display Con 1
CON8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
8
0
To ECR (Overcapacity, CON 7 Pin#20 )
0.5%
10K
L9,10,11
TDK221 X 3
R10
0.5%
10k
CAPTURE (From A/D)
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