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Cisco AS5350 - Universal Access Server - Page 38

Cisco AS5350 - Universal Access Server
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2-4
Cisco AS5350 and Cisco AS5400 Universal Gateway Software Configuration Guide
OL-3418-02 B0
Chapter2 Verifying Basic Setup
Analyzing the System Boot Dialog
00:01:10: %TRUNK_CLOCK-6-BAD_CLOCKS: There are no good clocks in the system. Remain in
HOLDOVER mode
00:01:10: %TRUNK_CLOCK-6-BAD_CLOCKS: There are no good clocks in the system. Remain in
HOLDOVER mode
Step 5 Enter the show version command to check the system hardware, Cisco IOS image name, uptime, and
restart reason:
Router> show version
Cisco Internetwork Operating System Software
IOS (tm) 5350 Software (C5350-JS-M), Version 12.1(20001028:174051)]
Copyright (c) 1986-2001 by cisco Systems, Inc.
Compiled Mon 19-Feb-01 04:10 by
Image text-base: 0x60008968, data-base: 0x61180000
ROM: System Bootstrap, Version 12.0(19991122:230447)
BOOTFLASH: 5350 Software (C5350-BOOT-M), Version 12.0(19991112:131]
AS5400 uptime is 1 day, 4 hours, 29 minutes
System returned to ROM by reload at 12:34:33 UTC Tue Nov 30 1999
System image file is "flash:c5350-js-mz.xm.Feb19"
cisco AS5400 (R7K) processor (revision L) with 131072K/65536K bytes of memory.
Processor board ID 99290068
R7000 CPU at 250Mhz, Implementation 39, Rev 1.0, 256KB L2, 2048KB L3 Cache
Last reset from warm-reset
Bridging software.
X.25 software, Version 3.0.0.
SuperLAT software (copyright 1990 by Meridian Technology Corp).
TN3270 Emulation software.
Primary Rate ISDN software, Version 1.1.
Manufacture Cookie Info:
EEPROM Type 0x0001, EEPROM Version 0x01, Board ID 0x31,
Board Hardware Version 1.21, Item Number 800-5171-01,
Board Revision 011, Serial Number 99290068,
PLD/ISP Version 0.0, Manufacture Date 2-Aug-1999.
Processor 0xFF, MAC Address 0x0503EFF5F4C
Backplane HW Revision FF.FF, Flash Type 5V
2 FastEthernet/IEEE 802.3 interface(s)
2 Serial network interface(s)
108 terminal line(s)
8 Channelized T1/PRI port(s)
512K bytes of non-volatile configuration memory.
16384K bytes of processor board System flash (Read/Write)
8192K bytes of processor board Boot flash (Read/Write)
Configuration register is 0x2102
Table 2-1 describes the significant output fields in the previous example.

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