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Cisco CRS-1 Carrier Routing System to Cisco CRS-3 Carrier Routing System Migration Guide
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Chapter 3 Cisco CRS-3 Carrier Routing System Router Command Changes
show controllers (Ethernet)
spi4_tx_frames: SPI-4/1 transmit frame count. This counter increments once for
every packet arriving on the SPI-4.2 receive interface.
Note Packets that contain certain types of errors and packets sent
to the CPU are not counted.
DeviceID Unique number identifying the device.
RevisionID Indicates the revision of the device.
SideBandFC Indicates whether serial sideband flow control is enabled on this
port, and the status of ports where flow control is currently active.
SERDESGlbCntl Displays information about SERDES speed and receive (Rx) Gain
on this port.
GlblEPDCntlCfg Cisco-specific register that shows whether Ethernet Packet
Decoding is enabled.
TxFIFOUrecECCErrCtr Transmit (Tx) FIFO unrecoverable ECC errors counter. This
counter increments once per each ECC unrecoverable error. A
masked interrupt is optionally generated.
RxFIFOUrecECCErrCtr Receive (Rx) FIFO unrecoverable ECC errors counter. This counter
increments once per each ECC unrecoverable error. A masked
interrupt is optionally generated.
DeviceGlobalRst Global register that controls device reset state.
GlobalCfg Global register that controls enable, clock modes, and Rx Interface
behavior.
PortTest Port diagnostics register.
PL4IOGlblStat Register used during SPI4.2 initialization.
DeviceTest Diagnostic loopback register.
MACStatus Port0 MAC control port register.
MACControl0 Port0 MAC control port register. Indicates whether the port is enabled on
this port, and the status of flow control on this port.
MACControl1 Port0 MAC control port1 register. Indicates whether the port is enabled on
this port, and the status of flow control on this port.
MACControl2 Port0 MAC control port2 register. Indicates whether the port is enabled on
this port, and the status of flow control on this port.
SERDESCntl Port0 SERDES control port register. The following information is
displayed:
• 0 = 50 Ohm
• 1 = 75 Ohm
RateLimCntl Port0 Rate Limit control port 10 register.
SysIntMask When the matching bit in the mask register is reset, the matching
interrupt in the cause register is not included in the sum.
SysIntCause Register that tracks the causes of system interrupts.
GOPIntMask0 GOP interrupt Mask0. When the matching bit in the mask register
is reset, the matching cause in the GOP register is not included in
the sum.
Table 7 show controllers GigabitEthernet Field Descriptions
Field Description