R4910K_1%_04
C494
0.047u_10V_X7R_04
R409 140_1%_04
3.3VS
R331
4.99K_1%_04
R67 51_04
R4262_04
R333 25.5_1%_04
R329
1K_04
R51 *10mil_short
R308 51_04
R82 51_04
R52 56_1%_04
R41 *10mil_short
R309 51_04
R334 200_1%_04
R302 *10mil_s hort
Q24
MTN70 02ZH S3
G
DS
R84 *51_04
R327 *0_04
R50 *10mil_short
R76 51_04
BUF_CPU_RST#
1.5V
1.05VS_VTT 3,6, 25,26,27, 44,45,48
1.05VS_VTT
1.05VS_VTT
3.3V 3,7, 15,20,21,22,24, 25,26,27, 30,31,33, 37,38,41,43,44
DRAMRST_CNTRL 7,21
DDR3_DRAMRST# 10,11,12,13
1.5V 7,10,11,12,13,27,31,41,43
CLK_EXP_N 21
CLK_EXP_P 21
1.5VS_CPU 7,41
H_PROCHOT#45
CPUDRAMRST#
H_THRMTRIP#25
H_PECI25,35
H_PM_SYNC22
H_CPUPWRGD25
H_CPUPWRGD_R
XD P _ D B R _ R
SKTOCC#
CAD Note: Capacitor need to be placed
close to buffer output pin
S
D
G
Q37A
MTD N7 00 2Z H S6R
2
6
1
S
D
G
Q37 B
MTDN7002ZHS6R
5
3
4
C568 0.1u_16V_Y 5V_04
R521 130_1%_04
PMSYS_PWRGD _BUF VDDPWRGOOD_R
R97
10K_04
SM_RCOMP_2
SM_RCOMP_1
SM_RCOMP_0
PLT_RS T#2, 14,24
XDP_TRST#
XD P _ TC L K
H_PROCHOT#_D
H_CATERR#
XD P _ TM S
CPUDRAMRST#
XDP_PR EQ#
XD P _ TD I _ R
XD P _ TD O _ R
R328 1K _04
3.3VS
XD P _ D B R _ R
R3011K_04
S3 circuit:- DRAM_RST# to memory
should be high during S3
XD P _ PR D Y #
H_CPUPWRGD_R
CLOCKS
MISCTHERMALPWR MANAGEMENT
DDR3
MISC
JTAG & BPM
U32B
Iv y Bridge_rPGA_2DPC_R ev 0p61
SM_RCOMP[1]
A5
SM_RCOMP[2]
A4
SM_DR AMRST#
R8
SM_RCOMP[0]
AK1
BCLK#
A27
BCLK
A28
DPLL_REF_CLK#
A15
DPLL_REF_CLK
A16
CATERR#
AL33
PECI
AN33
PRO CHOT#
AL32
TH ER MTRI P#
AN32
SM_DRAMPWROK
V8
RESET#
AR33
PRD Y#
AP29
PREQ#
AP27
TCK
AR26
TMS
AR27
TRS T#
AP30
TDI
AR28
TDO
AP26
DBR#
AL35
BPM#[0]
AT28
BPM#[1]
AR29
BPM#[2]
AR30
BPM#[3]
AT30
BPM#[4]
AP32
BPM#[5]
AR31
BPM#[6]
AT31
BPM#[7]
AR32
PM_SY NC
AM34
SKTOCC#
AN34
PRO C_SELEC T#
C26
UNCOREPWRGOOD
AP33
CLK_DP_P 21
DDR3 Compensation Signals
XD P_ TD O _R
TRACE WIDTH 10MIL, LENGTH <500MILS
PU/PD for JTAG signals
XD P_ TMS
BUF_CPU _RST#
CLK_DP_N 21
Processor Pullups/Pull downs
XDP_TRST#
H_PROCHOT#
XD P_ TC L K
XD P_ PR E Q#
XD P_ TD I _ R
SM_RCOMP_1
SM_RCOMP_0
SM_RCOMP_2
H_PROCHOT#_EC35
R34
100K_04
C60
68P_50V_NPO_04
R48
*750_1%_04
R38 *1.5K_1%_04
1.05VS_VTT
C306
*0. 1u_16V_Y5V_04
S3 circuit:- DRAM PWR GOOD logic
R193 0_04
U18
*MC74VH C1G08DF T1G
1
2
5
4
3
PM_DRAM_PWRGD22
3.3V
1.8VS_PWRGD22,44
PMSY S_PWR GD_BUF
R196
*200_04
R199
*100K_ 04
1.5VS_C PU
R322
200_1%_04
R325
*39_04
SUSB41,42,43,44
Q13
*MTN7002ZH S3
G
DS
3.3V
If PROCHOT# is not used,
then it must be terminated
with a 56-£[ +-5% pull-up
resistor to 1.05VS_VTT .
Ivy Bridge Processor 2/7 ( CLK,MISC,JTAG )
R511
100K_04
BSS138 ( VGS 1.5V )
H_PROCHOT#
PROC_SELET
R40 43_1%_04
P150HM_D04A
Buffered reset to CPU
C82
47P_50V_NPO_04
3.3VS 2,10, 11,12,13,14, 15,16,17,18, 19,20,21,22, 23,24,25,26,27,29,30,31,33, 34,35,36, 37,38,41,45,48
Q6
MTN7002ZHS3
G
DS
H_SNB_IVB#25
R39
75_04
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