5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCST_PWRGD
H_PROCHOT_EC
Close to CPU
SKL_CNL_N:
FLOAT FOR SKL
GND FOR CNL
CFG7
PEG Training:
1: (Default) PEG Train immediately following RESET# de assertion.
0: PEG Wait for BIOS for training
CFG[6:5]
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PCIE PORT BIFURCATION STRAPS
PLACE UNDER CPU
Close to CPU
CFG Hi Low DESCRIPTION
NORM Stall Ear
NORM Pchless Pchless Mode
NORM
Reverse PEG_LANE_REVERSAL-SEE PCIE CHAPTER
Enabled Disabled Physical_Debug_Enabled
Disable Enabled DP_Presence
Disable Enabled PEG0CFGSEL[0]
Disable Enabled PEG0CFGSEL[1]
Reset# BIOS REQ PEG_Defer_Training
Disable Enable CFG Unlock
Present Not Present SVID Not Present
10 Activate Not Activate Safe Mode Boot
11
Half-Swing
DC coupled
Full-Swing
AC coupled
DMI_AC_coupled
12 Pmsync2.0 Legacy
13 Asynchronous Synchronous Sync and Aync Mode
14 Reserved
15 Reserved
0
1
2
3
4
5
6
7
8
9
CFG4
1: Disabled
0: Enabled
eDP Enable:
CFG2
1: Normal operation
0: Lane numbers reversed
PCI Express* Static x16 Lane Numbering Reversal
CLOSE TO CPU
< 1.1"
CFG6 CFG5 PEG CONFIG
0V 0V X 8 X 4 X 4
0V 1V RESERVED
1V 0V X 8 X 8
1V 1V X 16
PEG CONFIG TABLE CFG [6:5] 11: Default X 16
10: 2X8
01: RESERVED
00: X8 , X4 , X4
* All CFG 0 = Physical Strap Hi
* All CFG 1 = Physical Strap Lo
DIFF=85ohm, L=4"~9"
D02 0920 pwr debug
D02 0928 for PEG reverse
D02 1002 pwr debug
1.05V_VCCSTVDD3
1.05V_VCCSTG
3.3VA
1.05V_VCCST
1.05V_VCCST
H_PROCHOT_EC55
1.05V_VCCSTG7,65
VDD310,29,31,34,35,36,37,38,41,43,45,46,52,53,55,57,58,64,65,66,67,68,69,71,72,74,77,78
1.05V_VCCST7,37,38,65,71
3.3VA29,34,35,37,38,41,43,52,64,65,68,69
ALL_SYS_PWRGD10,43,55,64,71
PCH_CPU_BCLK_R_DN40
PCH_CPU_BCLK_R_DP40
PCH_CPU_PCIBCLK_R_DN40
PCH_CPU_PCIBCLK_R_DP40
CPU_24MHZ_R_DN40
CPU_24MHZ_R_DP40
H_PWRGD38
PLTRST_CPU#37
H_PM_SYNC37
H_TRST# 43
H_PREQ# 43
H_THERMTRIP#37
H_SKTOCC_N39
H_PRDY# 43
H_TDO 38
H_TDI 38
H_TMS 38
H_TCK 38
H_PROCHOT#71
H_PM_DOWN37
H_CPU_SVIDCLK71
H_CPU_SVIDDAT71
H_CPU_SVIDALRT#71
H_PECI55
DDR_VTT_PG_CTRL68
Title
Size Document Number Rev
Date: Sheet
of
6-71-PB500-D03
D03
[02-3] CPU E/13 CLK,JTAG
A3
491Friday, December 07, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50EF
Title
Size Document Number Rev
Date: Sheet
of
6-71-PB500-D03
D03
[02-3] CPU E/13 CLK,JTAG
A3
491Friday, December 07, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50EF
Title
Size Document Number Rev
Date: Sheet
of
6-71-PB500-D03
D03
[02-3] CPU E/13 CLK,JTAG
A3
491Friday, December 07, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50EF
R541 499_1%_04
R875 *0402_short-p
C1337
*0.1u_10V_X5R_04
C1335
*0.1u_10V_X5R_04
R546 1K_04
R544 51_04
R547
*100K_04
R876 *0402_short-p
R542 51_04
R106 1K_04
C1293 *0.1u_10V_X5R_04
R543
1K_04
R105 56.2_1%_04
5 OF 13
U38E
CFL_H_62_INT_IP_CRB_CFLH/BGA
VIDSOUT
BH29
DDR_VTT_CNTL
BT13
VCCST_PWRGD
H13
PM_SYNC
BM34
PM_DOWN
BP31
PECI
BT34
CFG_18
BN22
PROC_TCK
BR28
CFG_19
BP22
THERMTRIP#
J31
PROC_TDO
BT28
CFG_0
BN25
PROC_TRST#
BP30
CFG_1
BN27
PROC_SELECT#
BN1
ZVM#
AT13
SKTOCC#
BR33
CFG_2
BN26
CFG_RCOMP
BT25
CFG_3
BN28
PROC_PREQ#
BL30
CFG_4
BR20
CFG_10
BT23
RESET#
BP35
CFG_5
BM20
CLK24N
D31
PROCPWRGD
BT31
CFG_11
BT22
CFG_6
BT20
BPM#_0
BR27
VIDSCK
BH32
BCLKN
A32
PCI_BCLKN
C36
BPM#_1
BT27
CFG_7
BP20
CFG_12
BM19
CLK24P
E31
CFG_8
BR23
CFG_13
BR19
BPM#_2
BM31
BCLKP
B31
PCI_BCLKP
D35
BPM#_3
BT30
PROCHOT#
BR30
CFG_9
BR22
CFG_14
BP19
RSVD2
AY13
CFG_15
BT19
RSVD1
AU13
PROC_PRDY#
BP27
CFG_16
BP23
CATERR#
BM30
PROC_TDI
BL32
MSM#
AW13
PROC_TMS
BP28
CFG_17
BN23
VIDALERT#
BH31
R585 60.4_1%_04
R100 220_04
S
D
G
Q51A
MTDK3S6R
2
61
R540 20_1%_04
R577 *0_04
R104 100_04
S
D
G
Q51B
MTDK3S6R
5
34
R549 *1K_04
Q43
UK3018 2.5V drive
G
DS
R867
*0402_short-p
R539 100K_04
R548 *1K_04
R574
100K_04
R545 49.9_1%_04
R575
1K_04
R537 *0402_short-p
H_PROCHOT#
VCCST_PWRGD
SKL_CNL_N
SKL_XDP_MBP_0
SKL_XDP_MBP_1
SKL_MBP_2
SKL_MBP_3
H_TDO
H_TCK
CFG_RCOMP
VCCST_PWRGD
H_VIDALERT_N
H_PECI_R
CFG4
H_PROCHOT#_R
VCCST_PWRGD_R
H_PROCHOT#
H_PM_DOWN_R
CFG5
CFG6
CFG7
CFG0
H_TDO
H_TCK
CFG2
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