5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BIOS ROM 128MB
SPI_* = 1"~6.5"
128Mbit / 3.3V
MXIC P/N = 6-04-25128-A72
Pin Straps(2)
RESERVED
External pull-up is required. Recommend
100K if pulled up to 3.3V or 75K if
pulled up to 1.8V.
This strap should sample HIGH. There
should NOT be any on-board device
driving it to opposite direction during
strap sampling.
ESPI FLASH SHARING MODE
LOW: MASTER ATTACHED FLASH SHARING (MAFS)
HIGH: SLAVE ATTACEHD FLASH SHARING (SAFS)
(INTERNAL WEAK PD)
CONSENT STRAP
ENABLE:LOW
PESONALITY STRAP
ENABLE:LOW
BOOT HALT
ENABLE:LOW
(INTERNAL WEAK PU)
JTAG ODT
DISABLE:LOW
(INTERNAL WEAK PU)
GPP_J5 : INTERNAL PU 20K
GPP_J7 : INTERNAL PU 20K
NVSR_DET# H : W/O NVSR Panel
L : W/ NVSR Panel
GSYNC_DET H : W/ GSYNC
L : W/O GSYNC
GSYNC_DET NVSR_DET
EDP
GSYNC
HH
L
BIOS setting
H
VCCPSPI VOLTAGE SELECT
LOW: 3.3V (DEFAULT)
HIGH: 1.8V
(INTERNAL WEAK PD)
20180424 Add to Control HDD RTD3
20180430 GPP_G5 Del PS8338B_SW
MLCC Comm part
close to PCH
close to PCH
20180509 Follow common design modify CNVi circuit
DIFF=85ohm, L<10"
To M.2
Zo=50ohm, L<10"
To M.2
20180521 RF check
20180613 modify 65987, delete TBTA_MRESET
20180717 Add ANX7411 Interrupt
20180720 Add
D01A 0829
Modify pwr plane
20180720 Add ANX7411 Interrupt
20180727
Change stuff location
20180727 ADD SPI TPM
20180727 ADD SPI TPM
D01A 0829
Change power plane
20180806
PCH use internal LDO
20180806
unstuff
D01A 0828 Add
D01A 0829
Modify pwr plane
D02 0921
D02 0926
D02 1005 Add
W/O TPM
W/ TPM
W/O TPM
W/ TPM
D02 1005
5.1ȍ to 0ȍ
D02A Del SD40 RTD3 function
VCC_RTC
SPI_3.3V
3.3VA
3.3VA
SPI_3.3V
SPI_3.3V
3.3VS
3.3VS
+V3.3A_V1.8A_VCCPGPPD
+V3.3A_V1.8A_VCCPGPPD
3.3VS
VDD3
3.3VA
+V3.3A_V1.8A_VCCPGPPD
3.3VS8,9,10,11,12,13,14,29,34,37,38,39,40,43,44,46,47,53,54,55,56,57,60,63,64,70,71,77
3.3VA4,29,34,37,38,41,43,52,64,65,68,69
VCC_RTC38,41
PLT_RST# 34,43
TBT_RTD3_PWR_EN_R 59
TBTA_HRESET 61
TBT_FORCE_PWR_R 59
PCH_GPP_K12 56
PCH_GPP_B3 56
NVSR_DET#10
GPP_J165,70
CNVI_BRI_DT45
CNVI_RGI_DT45
CNVI_RGI_RSP45
CNVI_BRI_RSP45
CNVI_GNSS_PA_BLANKING45
CNVI_MFUART2_RXD45
CNVI_MFUART2_TXD45
CNVI_WT_D1N 45
CNVI_WT_D1P 45
CNVI_WR_D0N 45
CNVI_WR_D0P 45
CNVI_WR_D1N 45
CNVI_WR_D1P 45
CNVI_WR_CLKN 45
CNVI_WR_CLKP 45
CNVI_WT_CLKN 45
CNVI_WT_CLKP 45
CNVI_WT_D0N 45
CNVI_WT_D0P 45
SWI#_GPP_G637
SATA_PWR_EN44
GPP_K15_INTP_OUT 51
GPP_K14_TEST_R 51
SPI_CS_2#52
+V3.3A_V1.8A_VCCPGPPD41,45
EC_SPI_CS_0# 55
EC_SPI_SCLK_R 55
EC_SPI_SO_R 55
EC_SPI_SI_R 55
SPI_3.3V41
VDD34,10,29,31,34,36,37,38,41,43,45,46,52,53,55,57,58,64,65,66,67,68,69,71,72,74,77,78
TPM_SPI_SCLK_R 52
TPM_SPI_SO_R 52
TPM_SPI_SI_R 52
Title
Size Document Number Rev
Date: Sheet
of
6-71-PB500-D03
D03
07-01-1 PCH A,M/13-SPI/SMB/CNVI
A3
35 91Friday, December 07, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50EF
Title
Size Document Number Rev
Date: Sheet
of
6-71-PB500-D03
D03
07-01-1 PCH A,M/13-SPI/SMB/CNVI
A3
35 91Friday, December 07, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50EF
Title
Size Document Number Rev
Date: Sheet
of
6-71-PB500-D03
D03
07-01-1 PCH A,M/13-SPI/SMB/CNVI
A3
35 91Friday, December 07, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50EF
R881 0_04
W/ TPM
R235 10K_04 W/O GSYNC
C1554
0.1u_6.3V_X5R_02
R853 0_04
W/ TPM
R381 33_04
R851 0_04
W/O TPM
R882 0_04
W/ TPM
R205 200_1%_04
R317 *4.7K_04
T90
R691 100_1%_04
R383 *100K_04
R389 *20K_04
R331 *10K_04
R731 10K_04
R674 *10K_04
R793 *1K_04
R347 *100K_04
R315 1M_04
R236 10K_04 W/ GSYNC
13 OF 13
U30M
HM370_MP
CNV_WR_CLKN
BD4
CNV_WR_CLKP
BE3
CNV_WR_D0N
BB3
CNV_WR_D0P
BB4
CNV_WR_D1N
BA3
CNV_WR_D1P
BA2
CNV_WT_CLKN
BC5
CNV_WT_CLKP
BB6
CNV_WT_D0N
BE6
CNV_WT_D0P
BD7
CNV_WT_D1N
BG6
CNV_WT_D1P
BF6
CNV_WT_RCOMP
BA1
GPPJ_RCOMP_1P81
BD1
GPPJ_RCOMP_1P82
BE1
GPP_J0/CNV_PA_BLANKING
AV6
GPP_I11/M2_SKT2_CFG0
AP3
GPP_G7/SD_WP
AV13
GPP_G5/SD_CD#
BE8
GPP_I12/M2_SKT2_CFG1
AP2
PCIE_RCOMPN
B12
GPP_J9/CNV_MFUART2_TXD
AU9
GPP_I13/M2_SKT2_CFG2
AN4
GPP_I14/M2_SKT2_CFG3
AM7
PCIE_RCOMPP
A13
GPP_G6/SD_CLK
BD8
GPP_J8/CNV_MFUART2_RXD
AW2
GPP_J10
AV7
TP
AL35
RSVD2
Y35
GPP_J11/A4WP_PRESENT
AR13
RSVD1
BC1
GPP_J2
AW3
GPP_G4/SD_DATA3
BG8
GPP_J3
AT10
GPP_J7/CNV_RGI_RSP/UART0B_CTS#
AV3
GPP_J1/CPU_C10_GATE#
AY3
GPP_J4/CNV_BRI_DT/UART0B_RTS#
AV4
SD_1P8_RCOMP
BE5
GPP_J5/CNV_BRI_RSP/UART0B_RXD
AY2
GPP_J6/CNV_RGI_DT/UART0B_TXD
BA4
SD_3P3_RCOMP
BE4
GPP_G3/SD_DATA2
BF9
GPPJ_RCOMP_1P83
BE2
GPP_G2/SD_DATA1
BF8
RSVD3
Y36
GPP_G0/SD_CMD
AW13
GPP_G1/SD_DATA0
BE9
R379 20K_04
R669 200_1%_04
R811 0_04
R868 10K_04
R204 200_1%_04
R382
33_04
T98
R215 20K_04
R214 33_04
R316 0_04
R362
*20K_04
R333 *4.7K_04
R813
20K_04
R794 *4.7K_04
R849 0_04
W/O TPM
R334 0_04
R823 33_04
R361
*20K_04
R812 33_04
R360 0_04
U61
MX25L12873F
CE#
1
SO
2
WP#
3
VSS
4
SI
5
SCK
6
HOLD#
7
VDD
8
R201 20K_04
1 OF 13
U30A
HM370_MP
SPI0_CLK
AW47
GPP_D22/SPI1_IO3
BC17
SPI0_MISO
BA45
SPI0_MOSI
AU41
GPP_K14/GSXDIN
W46
GPP_E3/CPU_GP0
AL47
GPP_H16/SML4CLK
AE43
GPP_B4/CPU_GP3
BC33
GPP_K16/GSXCLK
Y47
GPP_B3/CPU_GP2
BF32
GPP_E7/CPU_GP1
AM45
GPP_H17/SML4DATA
AJ46
SPI0_IO2
AY48
GPP_B13/PLTRST#
AV29
GPP_H14/SML3DATA
AD48
SPI0_IO3
BA46
SPI0_CS2#
AT40
GPP_H10/SML2CLK
AE48
GPP_H11/SML2DATA
AD47
SPI0_CS1#
AW48
GPP_K12/GSXDOUT
Y46
GPP_D21/SPI1_IO2
BD17
SPI0_CS0#
AY47
GPP_H18/SML4ALERT#
AE44
TP
AN35
GPP_H15/SML3ALERT#
AC47
GPP_K15/GSXSRESET#
AA45
GPP_K13/GSXSLOAD
Y48
RSVD1
R13
GPP_H13/SML3CLK
AF47
GPP_H12/SML2ALERT#
AB47
INTRUDER#
BB44
GPP_D0/SPI1_CS#/SBK0/BK0
BF19
GPP_D1/SPI1_CLK/SBK1/BK1
BE19
GPP_D3/SPI1_MOSI/SBK3/BK3
BF18
VSS_AL37
AL37
GPP_D2/SPI1_MISO/SBK2/BK2
BE18
RSVD2
R15
GPP_A11/PME#/SD_VDD2_PWR_EN#
BE36
R818
20K_04
R850 0_04
W/O TPM
R883 0_04
W/ TPM
R852 0_04
W/O TPM
R198 33_04
R819 33_04
R659 150_1%_04
R848 0_04
W/O TPM
SPI_SI_M
SPI_SO_M
SPI_SCLK_M
SPI_SI_R
SPI_SO_R
SPI_SCLK_R
SPI_CS_0#SPI_WP# SPI_CS0#
SPI_HOLD#
GPP_H12
GPP_H15
SPI_IO2
SPI_IO3
SPI_WP#
SPI_HOLD#
TBTA_MRESET
GPP_H15
GPP_H12
SPI_IO2
SPI_IO3
SPI_SI_R
SPI_SO_R
GPP_A11
GSYNC_DET
GPP_G1
NVSR_DET#
GPPJ_RCOMP_1P8
SD_RCOMP_3P3
SD_RCOMP_1P8
PCIECOMP_N
PCIECOMP_P
GPP_J1
CNVI_MFUART2_TXD
CNVI_BRI_DT_R
CNVI_RGI_DT_R
GSYNC_DET
NVSR_DET#
CNVI_MFUART2_TXD
CNVI_RGI_RSP
CNVI_BRI_RSP
SPI_SI_R
SPI_CS_0#
SPI_SCLK_R
SPI_SO_R
GPP_J1
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